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Debugging
The alt_max2.vo file resides in the labs/lab8/math/sdf directory.
2. Create the work library. Compile the post P&R Verilog netlist
(math_opt.vo) into the work library. The math_opt.vo file is located in the
labs/lab8/math/sdf directory.
3. Compile the testbench (math_opt_tb.vhd) into the work library. The
math_opt_tb.vhd file is located in the labs/lab8/math/src directory.
4. Simulate (vsim) the testbench math_opt_tb with the SDF maximum
timing switch (-sdfmax) along with specifying the correct instance to apply
to the SDF file.
The SDF file (math_opt.sdo) is located in the labs/lab8/math/sdf directory.
You will need to specify search library paths (-L switches for the altera
library and the work library) to allow ModelSim to find the Verilog cell
primitives located in the altera library.
5. Open the ModelSim wave window, add all top-level signals from the
testbench math_tb.
6. Turn on the performance profiler profile on and run the simulation for 5.13
us: time {run 5.13 us}
How long was the ModelSim runtime for the Verilog gate-level SDF
simulation? __________
(move the decimal point 6 places to get the number of seconds)
Is this runtime less than what you observed in the non-optimized Verilog
design? __________
How much slower or faster was the optimized Verilog runtime vs. nonoptimized Verilog? __________
7. Quit ModelSim when completed (quit -f).
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ModelSim Advanced Debugging
December 2002