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MPC7451 Microprocessor: Architectural Implementation
Table 1-1. Register Summary for MPC7451 (continued)
Reference /
Section
Name
SPR
Description
PTEHI,
PTELO
981,
982
The PTEHI and PTELO registers are used by the tlbld and tlbli
instructions to create a TLB entry. When software table searching
is enabled (HID0[STEN] = 1), and a TLB miss exception occurs,
the bits of the page table entry (PTE) for this access are located
by software and saved in the PTE registers.
2.1.5.7.2,
5.5.5.1.2
PVR
287
Processor version register. Read-only register that identifies the
version (model) and revision level of the processor.
PEM,
2.1.4.1
SDAR,
USDAR
—
Sampled data address register. The MPC7451 does not
implement the optional registers (SDAR or the user-level,
read-only USDAR register) defined by the PowerPC architecture.
Note that in previous processors the SDA and USDA registers
could be written to by boot code without causing an exception,
this is not the case in the MPC7451. A mtspr or mfspr SDAR or
USDAR instruction causes a program exception.
2.1.5.9.12
SDR1 18
25
Sample data register. Specifies the base address of the page
table entry group (PTEG) address used in virtual-to-physical
address translation.
Implementation Note—The SDR1 register has been modified
(with the SDR1[HTABEXT] and SDR1[HTMEXT] fields) for the
MPC7451 to support the extended 36-bit physical address (when
HID0[XAEN] = 1]).
PEM,
2.1.3.5,
5.5.1
SIAR 4
955
Sampled instruction address register. Contains the effective
address of an instruction executing at or around the time that the
processor signals the performance monitor exception condition.
USIAR provides user-level read access to the SIAR.
2.1.5.9.11
11.3.7
SPRG0–
SPRG3
SPRG4–
SPRG7 11
272–275
SPRGn. Provided for operating system use.
276-279
The SPRG4–7 provide additional registers to be used by system
software for software table searching.
SR0–
—
Segment registers (SRn). Note that the MPC7451 implements
separate instruction and data MMUs. It associates
architecture-defined SRs with the data MMU. It reflects SRs
values in separate, shadow SRs in the instruction MMU.
26,
27
Machine status save/restore registers (SRRn). Used to save the
address of the instruction at which execution continues when rfi
executes at the end of an exception handler routine. SRR1 is
used to save machine status on exceptions and to restore
machine status when rfi executes.
Implementation Note—When a machine check exception
occurs, the MPC7451 sets one or more error bits in SRR1. Refer
to the individual exceptions for individual SRR1 bit settings.
SR15 19
SRR0,
SRR1
MOTOROLA
Chapter 1. Overview
PEM,
5.5.5.1.3
PEM
PEM,
2.1.3.4
4.3
1-43