Download MPC7450, MPC7451, MPC7441 Chip Errata

Errata No. 49: Missed snoop transaction due to ignored QACK deassertion
during transition to low power mode
Description:
A deassertion of QACK will be ignored for a certain number of cycles after entering nap mode. A snoop
transaction presented during this time will not be serviced and may cause memory incoherency or
processor hangs.
Upon entering a low power mode (nap or sleep), the L3 interface is powered down. However, read errors
can result if the system attempts to wake the processor before the L3 has been properly powered down (see
Error 39 in the MPC7450 Family Chip Errata for the MPC7451, MPC7450, and MPC7441). To prevent
these errors, the processor enters a protected time window during which it ignores the state of the QACK
signal while it powers down the L3. This window exists when L3CR[L3CLK] is set and does not depend
on L3CR[L3E]. A consequence of this protected window is that the processor will remain in the low power
mode for a minimum period of time. During this time, the processor cannot be awakened by deasserting
QACK and is unable to snoop bus transactions. The processor will recognize the deassertion of QACK at
the end of the protected period, however, if QACK is held deasserted.
Note: There is an eight-bus cycle period required after the deassertion of QACK for the processor to
transition from nap or sleep mode to doze mode (see the MPC7450 RISC Microprocessor Family User’s
Manual). This requirement is separate from the minimum time period described herein, therefore, TS must
not be asserted until eight cycles after the expiration of that period. Asserting TS for a snoop transaction
too early will cause the transaction to be ignored, possibly resulting in memory incoherency or a hang
condition.
Projected Impact:
Systems using the L3 interface and power management modes may experience memory corruption or
hangs.
Work-Around:
Do not issue a transaction the processor must snoop until eight bus cycles after the protection window
expires. The length of the protected window is measured in bus cycle and is determined by both the
bus:core clock ratio and the core:L3 clock ratio, as shown in Table 6.
Table 6. Protection Window Duration (Bus Cycles)
Bus:Core
Ratio
Core:L3 Ratio
2
2.5
3
3.5
4
5
6
2
25
33
31
41
38
45
52
2.5
20
27
25
33
30
36
42
3
17
22
21
28
25
30
35
3.5
14
19
18
24
22
26
30
4
13
17
16
21
19
23
26
4.5
11
15
14
19
17
20
23
5
10
14
13
17
15
18
21
MPC7451 Chip Errata, Rev. 20
Freescale Semiconductor
63