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Fail Safe Mechanisms
C540U / C541U
8.2.1 Functionality of the Oscillator Watchdog Unit
Figure 8-2 shows the block diagram of the oscillator watchdog unit. It consists of an internal RC
oscillator which provides the reference frequency for the comparison with the frequency of the onchip oscillator.
EWPD
(PCON1.7)
WS
(PCON1.4)
Power - Down
Mode Activated
Power-Down Mode
Wake - Up Interrupt
Activity on
USB Bus
P3.2 / INT0
Control
Logic
Control
Logic
Internal Reset
Start /
Stop
RC
Oscillator
f RC
3 MHz
Start /
Stop
XTAL1
XTAL2
10
f1
f2
Frequency
Comparator
f 2 <f 1
Delay
On-Chip
Oscillator
>1
WDCON (C0 H )
OWDS
Int. Clock
MCD03385
Figure 8-2
Functional Block Diagram of the Oscillator Watchdog
The frequency coming from the RC oscillator is divided by 10 and compared to the on-chip
oscillator's frequency. If the frequency coming from the on-chip oscillator is found lower than the
frequency derived from the RC oscillator the watchdog detects a failure condition (the oscillation at
the on-chip oscillator could stop because of crystal damage etc.). In this case it switches the input
of the internal clock system to the output of the RC oscillator. This means that the part is being
clocked even if the on-chip oscillator has stopped or has not yet started. At the same time the
watchdog activates the internal reset in order to bring the C540U/C541U in its defined reset state.
The reset is performed because a clock is available from the RC oscillator. This internal watchdog
reset has the same effects as an externally applied reset signal with the following exceptions: The
watchdog timer status flag WDTS is not reset (the watchdog timer however is stopped) and bit
OWDS is set. This allows the software to examine error conditions detected by the watchdog timer
even if meanwhile an oscillator failure occured.
Semiconductor Group
8-6
1997-10-01