Download MPC850CE: MPC850 Device Errata Reference

GLOBAL ERRATUM
Part 1 MPC850 Revision C- Mask Set 0K44m
Version(s): MPC850, MPC850DE, MPC850DSL, MPC850SR
[Asterisks (*) indicate errata scheduled for fix in the next revision. Carats (^) indicate errata that will not be
corrected due to minimal system impact and/or availability of simple workarounds. No indication indicates
errata for which fixes have not been scheduled.]
1.1
GLOBAL ERRATUM
^GLL1. Some registers are not initialized correctly during Power-Up RESET, HRESET*, and SRESET*.
1.2
SIU ERRATA
SIU1. Spurious External Bus Transaction Following PLPRCR Write.
SIU4. Possible External Bus Hang Occurs Under Certain Error Conditions.
^SIU10. RTC/PIT doesn't count properly.
1.3
CPM ERRATA
CPM14. The ERAM4K Bit in the RISC Microcode Development Support Control Register (RMDS) is
Erroneously Cleared.
CPM15. USB underrun when ATM or Ethernet function is used in conjunction with USB.
1.4
GENERAL ERRATA
G1. Core Operation is Limited to a 3.0V Minimum.
G7. Restriction of open collector pull up.
1.5
CPU ERRATA
CPU1. Bus Error Unsupported by the Data Cache Burst.
CPU3. Incorrect Data Breakpoint Detection on Store Instructions.
CPU4. Program Trace Mechanism Error.
CPU6. Instruction MMU Bug at Page Boundaries in Show-all Mode.
^CPU11. Possible Excess Current Consumption in Deep Sleep Mode.
1.6
ATM ERRATA
ATM1. APCO Interrupts Cannot Be Masked.
*ATM2. CPM Lockup When Issuing APC_BYPASS When TX Queue Full.
2
MPC850 Device Errata Reference
MOTOROLA