Download XC27x5X Derivatives

XC27x5X Derivatives
System Units (Vol. 1 of 2)
Memory Checker Module (MCHK)
Note: The MATCH output is connected to an external port in packaged devices with 144
or more pins only.
4.2
Functional Description
Conventional digital processing systems generally are configured around volatile and
non-volatile memory elements. These memories provide (store) the data and
instructions to the CPU doing the main computing of an embedded system. This includes
the administration of the system by coordinating the operation of various system units to
perform system tasks.
Faults within these memories are in general critical for the safety and reliability of an
embedded system. Therefore these memories have mechanisms to check for data
consistency, e.g. parity or ECC (error correction code). These mechanisms can detect
faults up to a certain amount (e.g. double bit faults) per word (bit line faults).
Concatenated codes (block codes, word codes) can also detect multibit faults per word
(word line faults), which increases the fault coverage.
The MCHK is a parallel signature compression circuitry that calculates a concatenated
CRC block code to increase test coverage by code concatenation. This enables error
detection within a block of data stored in memory, registers, or communicated e.g. via
serial communication lines. The MCHK reduces the probability of error masking due to
repeated error patterns by compressing parallel test inputs from a block of data to be
tested. Furthermore, it can generate pseudo random numbers.
The MCHK uses a multiple input linear feedback shift register to generate a checksum
(signature) of a block of data. A multiple input linear feedback shift register (MISR) is a
shift register whose internal feedback input bit is driven by the exclusive-or (XOR) of
some bits of the overall shift register value (LFSR: linear feedback shift register).
This generator includes an arithmetic circuitry to calculate the block code. This circuitry
is implemented as an independent piece of hardware and, therefore, does not rely on the
memories to be tested. Only for the configuration it requires initialization data out of the
memories. To avoid the need of a multi master system (CPU, DMA, etc.), the CPU (e.g.
PEC, subroutine) is used to handle the data read and write transactions. These
transactions rely on the memories to be tested because they may contain the respective
CPU instruction code. Therefore the MCHK implements additional measures to enable
detection of erroneous data move operations by the CPU.
The following error scenarios are detected:
•
•
•
•
The CPU configures the MCHK erroneously
The CPU does not provide the data from the respective address range
The CPU does not provide the correct amount of data
The CPU is not able to check correctly the match of the online generated CRC block
code and the expected offline (during development) generated CRC block code
User’s Manual
MCHK, V1.10
4-2
V1.2, 2008-09