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Communication Processor Module 16.15.9 SMC Interrupt Handling The following list describes what normally occurs within an SMC interrupt handler: 1. Once an interrupt occurs, read the SMCE register to see which sources caused interrupts. The SMCE bits are usually cleared at this time. 2. Process the Tx BD to reuse it if the TX bit is set in the SMCE register. Extract data from the Rx BD if the RX bit is set in the SMCE. To transmit another buffer, simply set the Tx BD R-bit. 3. Clear the SMC1 bit in the CISR. 4. Execute the RFI instruction. 16.15.10 SMC as a Transparent Controller 16.15.10.1 FEATURES. The following is a list of the SMC transparent controller’s important features: • Flexible data buffers • Can be used to connect to a TDM bus using the TSA in the serial interface • Transmits and receives transparently on it’s own set of pins using a sync pin to synchronize the beginning of transmission and reception to an external event • Programmable character length (4–16) • Reverse data mode • Continuous transmission and reception modes • Four commands 16.15.10.2 SMC TRANSPARENT COMPARISON. As compared to the transparent modes supported by the SCCs, the SMCs offer less functionality. This fits with their purpose of providing simpler functions and slower speeds. The following is a list of features the SMC transparent controller does not support: • Independent transmit and receive clocks, unless connected to a TDM channel of the serial interface • CRC generation and checking • Full RTS, CTS, and CD pins (supports only one SMSYN pin) • Ability to transmit data on demand using the TODR • Receiver/transmitter in transparent mode while executing another protocol • 4-, 8-, or 16-bit SYNC recognition • Internal DPLL support • Other features for the SCCs as described in the GSMR 16-360 MPC821 USER’S MANUAL MOTOROLA
