Download BR101/D - Curiosity Killed the Cat

DSP96002 Interface Techniques and
Examples
Conference Bridging in the Digital
Telecomms Environment Using the
Motorola DSP56000
Describes DSP96002 interfacing in four situations: Three
high performance interconnection techniques for two or
more DSP96002s; Connecting the DSP96002 as an Attached
Processor on the IBM PC/AT™ bus (ISA bus) to provide
an IEEE floating-point numeric accelerator; Interfacing the
DSP96002 to the VMEbus by making an ADS96002 board
a VMEbus slave; and Interfacing the DSP96002 to two
DSP56ADC16 Sigma-Delta A/D converters. Timing diagrams
and program listings are provided where necessary. A
final section describes a non-intrusive hardware cycle counter
for the DSP96002 Application Development System.
Conference Bridging allows telephone calls of three or
more subscribers to be set up, and provides arbitration so
that conversation can take place in a controlled manner.
Digital bridges usually use a ‘single speaker’ algorithm to
preserve good signal to noise ratio, with the loudest speaking subscriber being selected as the current speaker.
This scheme is a software implementation written for the
DSP56000/1.
Order by: APR14/D
Order by: APR10/D
Implementation of Adaptive Controllers on
the Motorola DSP56000/DSP56001
DSP56001 Interface Techniques and
Examples
An adaptive control system measures a certain performance
rating. Based on the difference between desired and
measured performance, the adjustment system modifies
the parameters of the adaptive controller and the control
law in order to maintain performance close to the desired
value. This note shows how the DSP56000/DSP56001
digital signal processors can be used to solve real-time
digital control problems. After reviewing the basic theory
of adaptive control, it describes a number of implementations
using serial-parallel reference models.
Rev 1
The cost of using SRAM to create a large memory for a
DSP system can be prohibitive. Pseudo Static RAM (PSRAM)
– which combines a dynamic RAM array with a simple
interface and on-chip refresh logic – provides a compromise
between high density, low cost, high speed and interface
simplicity. This note presents a simple implementation of a
PSRAM interface to the DSP56001. It also describes an
interface with standard dynamic RAM for systems needing
large amounts of memory, such as audio special effects.
The final section shows an interface with an ISA Bus host
processor that uses only two additional parts.
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Calculating Timing Requirements of
External SRAM for the 24-bit DSP56000
Family
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Twin CODEC Expansion Board for the
DSP56000 Application Development
System
When interfacing the DSP56000 family Digital Signal
Processors to external SRAM, the behaviour of the internal
clock is affected by the external clock and by the configuration
of the Phase Locked Loop. This behaviour in turn determines
the speed requirement of the external SRAM. Timing
parameters are also affected by the configuration of the
signals that the DSP uses to access the SRAM. This note
is a tutorial on calculating the timing requirements. The
examples and discussion are based on the DSP56002,
but may also be applied to other members of the DSP56000
family having an external bus.
This twin CODEC board is designed to simplify the
development of telecom applications based on the DSP56000
Family processors. It uses the standard telecom sampling
frequency of 8KHz, and the filter has a 300Hz to 3.4KHz
band-pass characteristic. The board interfaces directly
with the DSP using the SSI interface and is intended for
any situation where a DSP module is required to link two
analogue lines. Includes PCB artwork and DSP software
listings for conversion between data formats.
Order by: APR16/D
Order by: APR12/D
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