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The Capture/Compare Unit CAPCOM6
C164CI
Shadow Latches for Synchronous Update
The timer period, offset and compare values are written to shadow latches rather than to the actual
registers. Thus the values for a new output signal can be programmed without disturbing the
currently generated signal(s). The transfer from the latches to the registers is enabled by setting the
respective shadow latch transfer enable bit STEx in register CTCON.
If the transfer is enabled the shadow latches are copied to the respective registers as soon as the
associated timer reaches the value zero the next time (being cleared in edge aligned mode or
counting down from 1 in center aligned mode).
When timer T12 is operating in center aligned mode it will also copy the latches (if enabled) if it
reaches the currently programmed period value (counting up).
After the transfer the respective bit STEx is cleared automatically.
Note: When starting timer T12 for the first time after reset the shadow latch transfer is done
automatically. For timer T13 bit STE13=’1’ is also required for the first start.
Note: If a new compare value is written to the shadow latches while T12 is counting up, the new
value must be smaller than the current period value. Otherwise no more matches will be
detected and the output signals will not change any more.
If a compare value is written, while T12 is counting down, any value may be used.
Semiconductor Group
17-19
Version 1.0, 11.97