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Download IBM PowerPC 750CX/750CXe RISC Microprocessor User`s Manual
Transcript
Preliminary NOTE: All bidirectional signals are three-stated between bus tenures. The pipelining shown in Figure 8-18 can occur if the second access is not another load (for example, an instruction fetch). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 12 13 14 BR BG iABB TS A[0–31] CPU A CPU A CPU A TT[0–4] Read Read Read In In TBST GBL AACK ARTRY DBG iDBB D[0–63] Bad In TA DRTRY TEA 1 2 3 4 5 6 7 8 9 10 11 Figure 8-18. Single-Beat Reads Showing Data-Delay Controls Chapter 8. Bus Interface Operation 3/15/01 Page 8-29
