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Digital Device Reference 143 rise_delay Rise delay real 1.00E-09 1e-12 - INF fall_delay Fall delay real 1.00E-09 1e-12 - INF sr_load S & r load values (F) real 1.00E-12 none enable_load Clk load value (F) real 1.00E-12 none set_load Set load value (F) real 1.00E-12 none reset_load Reset load value (F) real 1.00E-12 none family Logic family string UNIV none in_family Input logic family string UNIV none out_family Output logic family string UNIV none out_res Digital output resistance real 100 0 - INF out_res_pos Digital O/P Res pos slope real out_res 0 - INF out_res_neg Digital O/P Res neg slope real out_res 0 - INF min_sink Minimum sink current real -0.001 none max_source Maximum source current real 0.001 none sink_current Input sink current real 0 none source_current Input source current real 0 none Device Operation This device is identical to the SR flip flop except that it is level not edge triggered. That is the output may change whenever the enable input is high. State Machine Schematic Entry: Example Part Spice.cml Netlist entry: Axxxx [ in_0 in_1 .. in_n ] clk reset [ out_0 out_1 .. out_n ] model_name Connection details: Name Description Flow Type Vector bounds in Input in d, vector none clk Clock in d n/a reset Reset in d n/a out Output out d 1 - no upper bound Model format: .MODEL model_name d_state parameters
