Download Verification Intellectual Property (IP) Modeling Architecture

Verification IP Modeling Architecture
version 1.1
Note that in the example above, the c_io_rd and c_io_wr methods could be defined in a separate class or in
the same class, or be part of the BFM class itself.
One other advanced method to introduce a higher level of randomization is to use Vera sequence
generation feature in conjunction with the above mentioned class structure, in this case the cmd_operation
class. A sample code follows:
Example 13: Example of Vera Sequence Generator (VSG), randomizing PCI commands
….
class Syn_Pci_cmd_generator
{
….
Syn_Pci_cmd_operation opr;
….//other variables
task new(…);
task set_dist_param(..);
task set_cmd_seq(..);
..
}
..
..
task Syn_Pci_cmd_generator::set_cmd_seq (..)
// other parameter settings
..
// here use the appropriate vsg style
randseq()
{
commands:
io_rd_prod | io_wr_prod |
mem_rd_multi_prod;
io_rd_prod: &(io_rd_cmd_w) io_rd_cmd;
io_rd_cmd:
{
opr.get_opr(IO_RD);
do_cmd(2, mstr);
};
io_wr_prod: &(io_wr_cmd_w) io_wr_cmd;
io_wr_cmd:
{
opr.get_opr(IO_WR);
do_cmd(3, mstr);
};
mem_rd_multi_prod: &(mem_rd_multi_cmd_w) mem_rd_multi_cmd;
mem_rd_multi_cmd: {
opr.get_opr(MEM_RD_MULTI);
do_cmd(12, mstr);
};
} // end of randseq
)
…..//other routines.
Resultant data and response from the design should be checked through check engine and appropriate selfchecking routines in this layer.
© Synopsys, Inc. 2001-2002
May 2002
Page 17 of 32