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Chapter 29 Random Number Generator (RNG) 29.1 Introduction This chapter describes the Random Number Generator (RNG), including a programming model, functional description, and application information. NOTE Please note that the MCF5232, MCF5233, and MCF5234 do NOT contain cryptography modules. Please refer to Table 1-1 for details on device configurations. 29.1.1 Overview The Random Number Generator (RNG) module is capable of generating 32-bit random numbers. It is designed to comply with FIPS-140 standards for randomness and non-determinism. The random bits are generated by clocking shift registers with clocks derived from ring oscillators. The configuration of the shift registers ensures statistically good data (i.e. data that looks random). The oscillators with their unknown frequencies provide the required entropy needed to create random data. 29.2 Memory Map/Register Definition The address map for the RNG module is shown in Table 29-1. Detailed register descriptions are found in the following section. Table 29-1. RNG Module Memory Map IPSBAR Offset Mnemonic [31:24] [23:16] [15:8] [7:0] Access 0x1A_0000 RNGCR RNG Control Register R/W 0x1A_0004 RNGSR RNG Status Register R 0x1A_0008 RNGER RNG Entropy Register W 0x1A_000C RNGOUT RNG Output FIFO R 29.2.1 RNG Control Register (RNGCR) Immediately following reset, the RNG begins generating entropy in its internal shift registers. Random data is not pushed to the output FIFO until after the GO bit in the RNGCR is set to a one. MCF5235 Reference Manual, Rev. 2 Freescale Semiconductor 29-1
