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Freescale Semiconductor, Inc. Interrupt Interface Table 9-12 Interrupt Priority Scheme (Continued) INTERNAL MODULE ICR REG Freescale Semiconductor, Inc... INTERRUPT LEVEL INTERRUPT SOURCE IL[2:0] IP[1] IP[0] 3 011 1 1 Internal Module 3 011 1 0 Internal Module 3 011 0 1 Internal Module 3 011 0 0 Internal Module 2 010 1 1 Internal Module 2 010 1 0 Internal Module 2 010 0 1 Internal Module 2 010 0 0 Internal Module 1 001 1 1 Internal Module 1 001 1 0 Internal Module 1 001 0 1 Internal Module 1 001 0 0 Internal Module Note: Multiple internal modules shall not be assigned to the same interrupt level and same interrupt priority when configuring the ICR registers. This can cause erratic chip behavior. 9.4.1.1 Interrupt Mask Register The IMR register is used to mask both internal and external interrupt sources from occurring. Table 9-13 Interrupt Mask Register (IMR) BITS 31 30 29 28 27 26 25 24 23 22 21 20 19 FIELD RESET — — — — — — — — — — — — — R/W BITS 15 14 13 12 11 FIELD DMA 1 DMA 0 UART 1 UART 0 I2C RESET 1 1 1 1 1 R/W 10 9 TIMER1 TIMER0 1 18 17 16 QSPI DMA 3 DMA 2 1 1 1 R/W R/W R/W 8 7 6 5 4 3 2 1 0 SWT — — — — — — — — 1 1 1 1 1 1 1 1 — 1 R/W ADDRESS MBAR (0 X 44) MOTOROLA System Integration Module For More Information On This Product, Go to: www.freescale.com 9-9
