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DMA Programming Model
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Table 14-12 DMA0REQ Field Definition
14.4.2
DMA0REQ(7:0)
FIELD VALUE
REQUEST SOURCE FOR DMA
BLOCK
0x80
DMA0: audio source 1
audio
0x81
DMA0: audio source 2
audio
0x00
reserved
0x01
reserved
0x02
reserved
0x03
reserved
0x04
reserved
0x05
reserved
0x06
reserved
0x07
reserved
0x08
reserved
0x09
reserved
0x0A
reserved
0x0B
reserved
0x0C
reserved
0x0D
reserved
0x0E
reserved
0x0F
reserved
SOURCE ADDRESS REGISTER
The source address register (SAR) is a 32-bit register containing the address from which the DMA
controller module requests data during a transfer.
Table 14-13 Source Address Register (SAR)
BITS
FIELD
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SAR3 SAR3 SAR2 SAR2 SAR2 SAR2 SAR2 SAR2 SAR2 SAR2 SAR2 SAR2 SAR1 SAR1 SAR1 SAR1
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BITS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIELD
14-8
31
SAR1 SAR1 SAR1 SAR1 SAR1 SAR1
SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 SAR1 SAR0
5
4
3
2
1
0
MCF5249UM
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