Download MCF5249 - Rockbox

Freescale Semiconductor, Inc.
Data Transfer Operation
A basic read bus cycle has six states (S0–S5). The signal timing relationship in the constituent states of a
basic read cycle is as follows:
Table 8-5 Read Cycle States
STATE
NAME
DESCRIPTION
STATE 0
The read cycle is initiated in state 0 (S0). On the rising edge of BCLK, the MCF5249 places a
valid address on the address bus and drives R/W high, if it is not already high.
STATE 1
The appropriate CS and OE are asserted on the falling edge of BCLK.
Freescale Semiconductor, Inc...
STATE 2
STATE 3
Data is made available by the external device and is sampled on the rising edge of BCLK
with /TA asserted. If /TA not asserted before the rising edge of BCLK at the end of the first
clock cycle, the MCF5249 inserts wait states (full clock cycles) until /TA is asserted. If
internal /TA is requested (auto-acknowledge enabled in the chip select control register,
CSCR) then /TA is generated internally by the chip select module.
STATE 4
During state 4, /TA should be negated by the external device or if auto-acknowledge is
enabled, negated internally by the chip select module.
STATE 5
CS and OE are negated on the falling edge of state 5 (S5). The MCF5249 stops driving the
address lines and R/W on the rising edge of BCLK, terminating the read cycle. The external
device must have its drive from the bus...' with 'The external device must stop driving the bus.
The rising edge of BCLK may be the start of state 0 for the next access cycle.
Note:
Note:
8.5.3
The external device has a maximum of 1.5 BCLK cycles after the start of S4 to three-state
the data bus after data is sampled in S3 during a read cycle. This applies to basic read
cycles and the last transfer of a burst.
The MCF5249 would not drive out data for a minimum of two BCLK cycles. However,
another slave device may start driving the bus as soon as its chip select is asserted. Chip
select may be asserted at the beginning of S1, so bus drive must stop before the end of
S0. Under these conditions, data contention on the bus would not exist.
WRITE CYCLE
The Write cycle as shown in Figure 8-6, will occur if the wait cycle field (WS) in the Chip Select Control
Register (CSR) is programmed to value “0000”. The CS low time is increased with n clocks if n is
programmed into the WS field.
During a write cycle, the MCF5249 sends data to the memory or to a peripheral device.
The write cycle flowchart is shown in the following figure, while the write cycle timing diagram is shown in
Figure 8-6.
8-8
MCF5249UM
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA