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Chapter 27
Intermediate Counter VIs
Delayed Pulse Generator Config
Configures a counter to generate a single, delayed TTL pulse on its OUT pin.
The signal is created by decrementing counter twice, first for the delay to the pulse (called
phase 1), then for the pulse itself (phase 2). If an internal timebase is chosen, the VI selects
the highest resolution timebase for counter to achieve the desired characteristics. If an
external timebase signal is chosen, the user designates the delay and width as cycles of that
signal. You can optionally gate or trigger the operation with a signal on counter’s GATE pin.
Call the Counter Start VI to start the pulse or enable it to be gated.
Down Counter or Divider Config
Configures the specified counter to count down or divide a signal on the counter’s SOURCE
pin or on an internal timebase signal using a count value called timebase divisor. The result
is that the signal on the counter’s OUT pin is equal to the frequency of the input signal divided
by timebase divisor.
You can use this VI to generate finite pulse trains by enabling a continuous pulse generator
until the desired number of pulses has occurred. You can also use it in place of the Continuous
Pulse Generator Config VI to generate a train of strobe or trigger signals.
LabVIEW Function and VI Reference Manual
27-4
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