Download Software driver for M32C/83`s GCI and HDLC feature

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Transcript 
APPLICATION NOTE
M16C Family
Software driver for M32C/83’s GCI and HDLC feature
1 Abstract
This application note describes the software driver, which is necessary in order to access the
M32C/83 function blocks for GCI/PCM and HDLC using applications. The software driver is
responsible for initialization and control of the hardware function blocks and for the setup of
the data transfer between the blocks.
2 Contents
1
Abstract .......................................................................................................................................... 1
2
Contents ......................................................................................................................................... 1
3
GCI/PCM interface ......................................................................................................................... 3
3.1
General Description of GCI/PCM ................................................................................................ 3
3.1.1
GCI TE mode...................................................................................................................... 3
3.1.2
GCI NT mode ..................................................................................................................... 4
3.1.3
PCM Highway mode........................................................................................................... 5
3.2
GCI interface support of M32C/83 .............................................................................................. 5
3.3
GCI Software Driver .................................................................................................................... 8
3.4
GCI Software Driver Flow diagram ............................................................................................. 9
4
3.4.1
Main() function.................................................................................................................. 10
3.4.2
SWD_GCI_RcvSndRdy() function.................................................................................... 11
3.4.3
Service_8KHZ() function .................................................................................................. 11
3.4.4
SWD_GCI_Init() function.................................................................................................. 12
3.4.5
SWD_GCI_SetRcv() function ........................................................................................... 13
3.4.6
SWD_GCI_SetSnd() function........................................................................................... 14
3.4.7
SWD_GCI_Start() function ............................................................................................... 15
3.4.8
SWD_GCI_Stop() function ............................................................................................... 15
HDLC feature................................................................................................................................ 16
4.1
General Description of HDLC ................................................................................................... 16
4.2
Intelligent I/O Group of M32C/83 .............................................................................................. 17
4.3
4.2.1
Basetimer clock generation .............................................................................................. 18
4.2.2
Receive HDLC unit ........................................................................................................... 19
4.2.3
Transmit HDLC unit .......................................................................................................... 20
HDLC Software Driver............................................................................................................... 22
4.3.1
Receive HDLC.................................................................................................................. 23
4.3.2
Transmit HDLC................................................................................................................. 24
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APPLICATION NOTE
M16C Family
Software driver for M32C/83’s GCI and HDLC feature
4.4
HDLC Software Driver Flow diagram........................................................................................ 25
4.4.1
Main() function.................................................................................................................. 26
4.4.2
Service_8KHZ() function .................................................................................................. 27
4.4.3
SWD_HDLC0_Basetimer_Init() function .......................................................................... 28
4.4.4
SWD_HDLC0_Init() .......................................................................................................... 29
4.4.5
SWD_HDLC0_RcvIn() function ........................................................................................ 30
4.4.6
SWD_HDLC0_RcvOut() function ..................................................................................... 31
4.4.7
SWD_HDLC0_RcvPoll() function ..................................................................................... 32
4.4.8
SWD_HDLC0_SndIn() function........................................................................................ 33
4.4.9
SWD_HDLC0_SndOut() function ..................................................................................... 34
4.4.10
5
6
SWD_HDLC0_SndPoll() function ................................................................................ 35
GCI-HDLC Driver C source code................................................................................................ 36
5.1
Main.c........................................................................................................................................ 36
5.2
SWD_GCI.h .............................................................................................................................. 39
5.3
SWD_GCI.c............................................................................................................................... 40
5.4
SWD_HDLC0.h ......................................................................................................................... 47
5.5
SWD_HDLC0.c ......................................................................................................................... 48
5.6
SWD_HDLC1.h ......................................................................................................................... 59
5.7
SWD_HDLC1.c ......................................................................................................................... 60
Reference ..................................................................................................................................... 73
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M16C Family
Software driver for M32C/83’s GCI and HDLC feature
3 GCI/PCM interface
3.1
General Description of GCI/PCM
The GCI (General Circuit Interface)/PCM (Pulse Code Modulation) highway standard defines
an industry-standard serial bus for interconnecting telecommunications ICs. This interface is a
pure physical interface. The serial bus GCI/PCM provides a full-duplex communication link
containing user control data, control/programming, and status channel. The data clock (DCL)
is used to clock data and operates at twice the data rate (except for PCM mode). The frames
are delimited by an 8-kHz frame sync signal (FSC). Dout/Din (data upstream/data
downstream) are the up/down serial information streams. The M32C/83 supports the
GCI/PCM interface in TE, NT and PCM highway mode.
3.1.1 GCI TE mode
The GCI TE mode is designed for ISDN terminal applications. The up/downstream data link
consists of three channels, each containing 32 bits. This 12 bytes frame is repeated at
8kHz, headed by a rising FSC signal, giving a data rate of 768kbit/s. Note that the DCL
frequency is 1.536MHz, so DCL have to be divided by the GCI interface of the M32C/83.
DCL
(1.536MHz
@ TE Mode)
FSC
Dout
B1
B2
Mon
Mr
D C/I
Mx
IC1
IC2
Mon
Mr
Mx
C/I
Din
B1
B2
Mon
Mr
D C/I
Mx
IC1
IC2
Mon
Mr
Mx
C/I
GCI Channel 0
GCI Channel 1
GCI Channel 2
Figure 1: GCI simplified timing diagram for TE mode
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M16C Family
Software driver for M32C/83’s GCI and HDLC feature
TE mode (fDCL= 1536kHz, fData = 768kHz)
Dout and Din are containing following data:
•
•
•
•
•
•
•
•
•
B1 :
Voice data or other data
8Bit
B2 :
Mon:
D:
Voice data or other data
Control data for layer 1 device
D channel control data
8Bit
8Bit
2Bit
C/ I:
MrMx:
IC1
IC‘s intercommunication (channel 0)
Handshake for Mon channel
IC‘s intercommunication
4Bit
2Bit
8Bit
IC2
C/ I:
IC‘s intercommunication
IC‘s intercommunication (channel 2)
8Bit
8Bit
3.1.2 GCI NT mode
The NT mode of the GCI interface provides a connection path between line transceivers
(ISDN) and codecs. The M32C/83 set into NT mode can act like a switch backbone. In this
mode ISDN transceiver and/or codecs/filters could be connected to the bus. Data, control and
status information is multiplexed into frames, which are transmitted in an 8kHz rate. One NT
frame is divided into 8 sub-frames, whereby one sub-frame is being dedicated to each
transceiver or pair of codecs.
DCL
(4.096MHz
@ NT Mode)
FSC
Dout
Din
M
B B
o
1 2
n
D
C/I
Mr
Mx
M D
M D
M D
M
B B
B B
C/I B B
C/I B B
o C/I
o
o
Mr 1 2
Mr 1 2
Mr 1 2 o
1 2
n Mx
n Mx
n Mx
n
D
C/I
Mr
Mx
M D
M
B B
B B
o C/I
Mr 1 2 o
1 2
n Mx
n
D
C/I
Mr
Mx
M
B B
o
1 2
n
D
C/I
Mr
Mx
M
B B
o
1 2
n
D
C/I
Mr
Mx
M D
M D
M D
M
B B
B B
B B
C/I B B
o C/I
o
o C/I
o
Mr
Mr
Mr
1 2
1 2
1 2
1 2
n Mx
n Mx
n Mx
n
D
C/I
Mr
Mx
M D
M
B B
B B
o C/I
o
Mr
1 2
1 2
n Mx
n
D
C/I
Mr
Mx
M
B B
o
1 2
n
D
C/I
Mr
Mx
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Figure 2: GCI simplified timing diagram for NT mode
NT Mode (fDCL = 4096kHz, fData = 2048kHz)
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M16C Family
Software driver for M32C/83’s GCI and HDLC feature
3.1.3 PCM Highway mode
The PCM Highway mode of the UART interface provides a connection path between line
transceivers (ISDN) and codecs. The M32C/83 set into PCM Highway mode can act like a
switch backbone. In this mode 32 slots of 8bit width are available, bounded by the 8kHz FSC
signal. Because the DCL frequency is equal to the data rate at the Data up/downstream lines,
DCL clock will not divided, by the internal functionality of the UART.
DCL
(2.048MHz @
PCM Mode)
FSC
Dout
Din
S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 3: GCI simplified timing diagram for PCM highway mode
PCM Mode (fDCL = 2048kHz, fData = 2048kHz)
3.2
GCI interface support of M32C/83
Because GCI intercommunication needs a pure serial interface, the UART2 of the M32C/83
supports the GCI functionality, by using an implemented hardware unit for GCI purpose. The
GCI unit of the M32C/83 generates the Data Clock by dividing the fDCL clock by two (except in
PCM highway mode). Additionally the data scanning of the DIN line or the data writing at DOUT
line can be synchronized to the rising edge of the FSC signal, using the synchronization
function of the GCI unit.
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M16C Family
Software driver for M32C/83’s GCI and HDLC feature
DCL
(Data Clock)
UART2: n-channel
open drain
UART Special Function
FSC
(Frame Sych.)
CLK2
Dout
(upstream)
UART2
Receive Buffer
Standard UART Block
Serial Synchronous mode
Din
(downstream)
UART2
Transmit Buffer
Figure 4: UART2 GCI interface schematic
Since Layer 1 is not implemented in the M32C/83, UART2 should be connected to a Layer1
device by following lines.
Function
Dout
Din
DCL
FSC
M32C/83 (144pin package)
TxD2
Port7.0
Pin37
RxD2
Port7.1
Pin36
CLK2
Port7.2
Pin35
CTS2
Port7.3
Pin34
M32C/83 (100pin package)
TxD2
Port7.0
Pin30
RxD2
Port7.1
Pin29
CLK2
Port7.2
Pin28
CTS2
Port7.3
Pin27
Table 1: GCI related pins of M32C/83
Using the PCM Highways three different kinds of timings can be used.
Referenced to the rising edge of DCL
Referenced to the falling edge of DCL
Referenced to the rising edge of DCL and FSC
To make clear the effect of the clock edge setting, please refer to figure 5. The M32C/83
satisfy with its simple and flexible timing opportunities, enabling the connectivity to most
available codecs and line interfaces.
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M16C Family
Software driver for M32C/83’s GCI and HDLC feature
Referenced to rising edge of DCL
DCL
FSC
Dout
Din
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Referenced to falling edge of DCL
DCL
FSC
Dout
Din
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Referenced to rising edge of DCL and FSC
DCL
FSC
Dout
Din
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Figure 5: PCM Highway timing settings
To fulfill the timing for the synchronization at rising edge of FSC and DCL, an external circuit is
required. This arrangement should generate a small delay (around some nsec) between rising
edge of DCL and FSC. To do so, different approaches are possible to delay the DCL signal,
e.g. RC filter or using some logical gates as delay line.
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M16C Family
Software driver for M32C/83’s GCI and HDLC feature
RC Filter
Din
C
DCL
R
OR
DCL
&
Logical Gate
delay time
P71
Dout
P70
FSC
P73
DCL
P72
M32C/83
Figure 6: Possible delay lines for DCL signal, if referenced to the rising edge of DCL and FSC
3.3
GCI Software Driver
The general transfer of data from GCI interface to RAM buffer or from RAM buffer to GCI is
handled by the DMA0 and DMA1 of the M32C/83. Thereby the DMA0 is initialized to transfer
the received data automatically from receive output register RxD2 to a shadow buffer system.
Moreover DMA1 is initialized to transfer the transmit data automatically from a shadow buffer
system, to transfer input register TxD2.
After a complete frame has been received by DMA0, an interrupt will be generated, where the
buffers of the shadow system for receive and transmit (no DMA1 interrupt is needed) will be
swapped. The shadow buffer for each communication direction consists of one array
(ucSWD_GCI_RcvBuffer, ucSWD_GCI_SndBuffer) and two pointers, whereby one of the
pointer contains the address of the first element of the array and the other is points to the
middle of this array.
The number of transferred bytes depends on the selected GCI mode support. In TE mode 12
bytes, in NT mode 32 bytes and in PCM Highway mode 32 bytes will be transferred by DMA,
before an interrupt is entered, to do the necessary pointer swapping.
Additional to the pointer rearrangement inside the interrupt routine SWD_GCI_RcvSndRdy, a
function call will be executed. The function call of this SWD_GCI_CallBackFunction, which is
actually a pointer to a user defined function, so modification of the driver itself is not necessary,
to extend the handling of the GCI data.
For this, a function is used as parameter for the SWD_GCI_Init() function call at the setup
process, whereby the selected function should include the user GCI data routing/handling.
Due to the logical link between FSC and DMA0 interrupt, the function will be entered every
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M16C Family
Software driver for M32C/83’s GCI and HDLC feature
125µsec. Therefore the function is called Service_8KHZ in this sample. Anyway, the user can
use an own function instead, just by referring to the function at the GCI init process.
The SWD_GCI_CallBackFunction call includes two pointers to the GCI buffers as parameter,
to allow access to the current up/down stream data.
Inside this routine the user can do all necessary reading, writing, modification or routing of the
different data bytes of the CGI data lines, by referring to the pointer plus the selected slot
number.
M32C/83
125us
UART2 Special Mode
FSC
DCL
Din
Dout
P73
CTS2
Request Bit
P72
CLK2
P71
RxD2
UART2 Receive
Buffer
DMA0
P70
TxD2
UART2
Transmit Buffer
DMA1
8kHz Interrupt Service
Routine after x bytes have
been processed
(switching, routing, etc.)
GCI Buffer for Receive
(+shadow buffer)
ucSWD_GCI_RcvBuffer
Byte 0
Byte1 0
Byte
Byte
. 1
. .
. .
. .
. .
. .
. .
Byte. x
Byte x
GCI Buffer for Transmit
(+shadow buffer)
ucSWD_GCI_SndBuffer
Byte 0
Byte1 0
Byte
Byte
. 1
. .
. .
. .
. .
. .
. .
Byte. x
Byte x
Figure 7: GCI driver concept
3.4
GCI Software Driver Flow diagram
The described Software Driver for GCI purpose is written in C-Source.
The GCI driver consists of SWD_GCI.c and SWD_GCI.h file. In the user code at least the
SWD_GCI_Init() and SWD_GCI_Start() functions have to be called. Additional a
Service_8KHZ function have to be implemented in the user code, which is the parameter of
the SWD_GCI_Init() call as well. The GCI mode can be selected in the SWD_GCI.c local
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M16C Family
Software driver for M32C/83’s GCI and HDLC feature
header part. Furthermore the synchronous behavior of the data lines signals regarding the
DCL signal can be selected there as well.
The following function will be used:
Functionname
Main()
SWD_GCI_RcvSndRdy()
Service_8KHZ()
SWD_GCI_Init().c
SWD_GCI_SetRcv()
SWD_GCI_SetSnd()
SWD_GCI_Start()
SWD_GCI_Stop()
Purpose
Main routine
DMA0 interrupt service routine
Interrupt Callback function of user
Initialization of GCI interface general
Initialization of GCI interface receive part (DMA0)
Initialization of GCI interface transmit part (DMA1)
Start of GCI function
Stop of GCI function
Table 2: Functions of the GCI software driver
3.4.1 Main() function
Function: main()
Start
SWD_GCI_Init
(SERVICE_8KHZ)
__enable_interrupt()
SWD_GCI_Start()
while(1)
Yes
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M16C Family
Software driver for M32C/83’s GCI and HDLC feature
3.4.2 SWD_GCI_RcvSndRdy() function
Interrupt Function: SWD_GCI_RcvSndRdy()
Start
SWD_GCI_CallBackFunction()
including pucSWD_GCI_McuToBuf and
pucSWD_GCI_BufToMcu as parameter
Swap the pointer
pucSWD_GCI_BufToUart and
pucSWD_GCI_McuToBuf
Set DMA1 source reload address to
pucSWD_GCI_BufToUart @ DRA1
register
Swap the pointer
pucSWD_GCI_UartToBuf and
pucSWD_GCI_BufToMcu
Set DMA0 destination reload address
to pucSWD_GCI_UartToBuf @
DRA0 register
End
3.4.3 Service_8KHZ() function
Function: Service_8KHZ()
Parameter: pucTransmit
pucReceive
Start
Write into the GCI upstream buffer,
with the help of pucTransmit pointer
Read out the GCI downstream buffer,
with the help of pucReceive pointer
End
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M16C Family
Software driver for M32C/83’s GCI and HDLC feature
3.4.4 SWD_GCI_Init() function
Function: SWD_GCI_Init()
Parameter: Pointer to user 8kHz function (ServiceFunction)
Start
Init Port pin relaited
registers (P7, PD7,
PS1, PSL1, PSC)
SWD_GCI_CallBackFunction =
ServiceFunction
SWD_GCI_SetSnd()
SWD_GCI_SetRcv()
Select Synchronous serial mode and
external clock @ U2MR register
No
#if GCI_MODE_TE
#if GCI_MODE_NT
#if GCI_MODE_PCM
Yes
Yes
#if
SYNCH_AT_RISING_DCL
No
Yes
Yes
Select MSB first, Transmit data at
rising edge, CTS/RTS disabled @
U2C0 register
#if GCI_MODE_PCM
#if
SYNCH_AT_FALLING_DCL
Select MSB first, Transmit data at
falling edge, CTS/RTS disabled @
U2C0 register
No
#if GCI_MODE_TE
#if GCI_MODE_NT
Yes
Yes
Select DCL clock not divided @
U2SMR register
#if GCI_MODE_PCM
Select LSB first, Transmit data at
rising edge, CTS/RTS disabled @
U2C0 register
Select DCL clock divided @ U2SMR
register
No
#if GCI_MODE_TE
#if GCI_MODE_NT
Yes
Yes
Select DCL Snchronous clock @
U2SMR2 register
Select DCL not Snchronous clock @
U2SMR2 register
End
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M16C Family
Software driver for M32C/83’s GCI and HDLC feature
3.4.5 SWD_GCI_SetRcv() function
Function: SWD_GCI_SetRcv()
Start
Disable DMA0 and DMA1@ DMD0
register
Select UART2 receive as DMA0
request cause trigger @ DM0SL
register
Initialization of
ucSWD_GCI_RcvBuffer with 0xFF
Set pointer pucSWD_GCI_UartToBuf
to begin of ucSWD_GCI_RcvBuffer
Set pointer pucSWD_GCI_BufToMcu
to middle of ucSWD_GCI_RcvBuffer
Set DMA0 destination address to
pucSWD_GCI_UartToBuf @ DMA0
register
Set DMA0 source address to UART2
receive buffer U2RB @ DSA0
register
Set DMA0 destination reload address
to pucSWD_GCI_BufToMcu @
DRA0 register
No
#if GCI_MODE_TE
Yes
#if GCI_MODE_PCM
#if GCI_MODE_NT
Yes
Set DMA0 count register to 12 bytes
@ DCT0 register
Set DMA0 count register to 31 bytes
@ DCT0 register
Set DMA0 count reload register to 12
bytes @ DRC0 register
Set DMA0 count reload register to 31
bytes @ DRC0 register
Enable DMA0 interrupt @ DM0IC
register
Swap the pointer
pucSWD_GCI_UartToBuf and
pucSWD_GCI_BufToMcu
End
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M16C Family
Software driver for M32C/83’s GCI and HDLC feature
3.4.6 SWD_GCI_SetSnd() function
Function: SWD_GCI_SetSnd()
Start
Disable DMA0 and DMA1@ DMD0
register
Select UART2 transmit as DMA1
request cause trigger @ DM1SL
register
Initialization of
ucSWD_GCI_SndBuffer with 0xFF
Set pointer pucSWD_GCI_BufToUart
to begin of ucSWD_GCI_SndBuffer
Set pointer pucSWD_GCI_McuToBuf
to middle of ucSWD_GCI_SndBuffer
Set DMA1 source address to
pucSWD_GCI_BuftToUart+1 @
DMA1 register
Set DMA1 destination address to
UART2 transmit buffer U2TB @
DSA1 register
Set DMA1 source reload address to
pucSWD_GCI_McuToBuf @ DRA1
register
No
#if GCI_MODE_TE
Yes
#if GCI_MODE_PCM
#if GCI_MODE_NT
Yes
Set DMA1 count register to 11 bytes
@ DCT1 register
Set DMA1 count register to 30 bytes
@ DCT1 register
Set DMA1 count reload register to 12
bytes @ DRC1 register
Set DMA1 count reload register to 31
bytes @ DRC1 register
Swap the pointer
pucSWD_GCI_BufToUart and
pucSWD_GCI_McuToBuf
End
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M16C Family
Software driver for M32C/83’s GCI and HDLC feature
3.4.7 SWD_GCI_Start() function
Function: SWD_GCI_Start()
Start
Reset the Resynchronization bit @
U2C1 register
Disable UART2 Receive and
Transmit @ U2C1 register
Reset UART2 serial I/O mode
selection @ U2MR register
Set UART2 serial I/O mode selection
to serial I/= mode @ U2MR register
Write dummy data into the transmit
buffer register of Uart2 @ U2TBL
register
Start DMA0 and DMA1 in repeat
mode @ DMD0 register
Enable Uart2 receive and transmit @
U2C1 register
End
3.4.8 SWD_GCI_Stop() function
Function: SWD_GCI_Stop()
Start
Disable DMA0 and DMA1 in repeat
mode @ DMD0 register
Disable UART2 Receive and
Transmit @ U2C1 register
SWD_GCI_Init() with
SWD_GCI_CallBackFunction as
parameter
End
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M16C Family
Software driver for M32C/83’s GCI and HDLC feature
4 HDLC feature
4.1
General Description of HDLC
HDLC is a universal standard error detecting protocol, which allows code transparent binary
transmissions of data. The job of the HDLC layer is to ensure that data, passed up to the next
layer, has been received exactly as transmitted (i.e. error free, without loss and in the correct
order). Another important job is flow control, which ensures that data is transmitted only as
fast as the receiver can receive it. The general purpose of this frame construct is to carry the
Layer 3 information.
A HDLC frame consists of different blocks.
Start Flag
Address
Field
Control
Field
Data Field
0111 1110
16 Bit
8/16 Bit
n x 8 Bit
Link Header
Layer 3
Information
Frame
Check
Sequence
16 Bit
End Flag
0111 1110
Link Trailer
Figure 8: Outline of HDLC frame
The beginning and end of an HDLC frame are marked by flag bytes “01111110” binary. No flag
character may appear within the frame. To enforce this requirement, the data may need to be
modified in a transparent manner. Therefore a binary 0 is inserted after every sequence of five
1s binary by the transmitter, this is called bit stuffing. Thus, the longest sequence of 1s of the
link that may appear is “0111110”, one less than the flag character.
The receiver, upon seeing five 1s, examines the next bit. If this bit is 0, the bit is discarded and
the frame continues. If it is 1, this must be the flag sequence at the end of the frame.
At the end of the frame, a Frame Check Sequence (FCS) is used to verify the data integrity.
The FCS is a CRC calculated using polynomial x16+x12+x5+1.
Between HDLC frames, the link idles. Most synchronous links constantly transmit data; these
links can transmit all 1s during the inter-frame period (called mark idle), or all flag characters
(called flag idle).
Usually when referring to HDLC in ISDN areas, people mean LAPD a deviate of HDLC
protocol. LAPD is a slightly modified version of HDLC.
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4.2
Intelligent I/O Group of M32C/83
For HDLC functionality the M32C/83 use two hardware implemented Intelligent I/O Groups.
Each of these two blocks provides a full-duplex HDLC channel includes following hardware to
realized HDLC functionality:
•
•
•
•
Zero-bit-deletion/insertion
CRC check according to CRC-CCITT
Start/end flag detection
Abort flag detection
This HDLC is a pure physical interface. It does not support any high-level layer functions.
The following block diagrams summarize the HDLC related portion from Intelligent I/O Group
0. The hardware realization for the Intelligent I/O Group 1 is transparent.
Each of these Intelligent I/O Groups can be segmented into following three blocks:
• Basetimer Clock generation
• Receive HDLC unit
• Transmit HDLC unit
f1
fPLL
Noise
Filter
Receive Input Buffer
(8bit)
Prescaler
Base Timer
PWM
Channel Wave Generation
Input Capture
Output Compare
Compare Register 0–4
CRC unit
Transmit Output Buffer
(8 bit)
LSB/MSB Selection
Compare Mask Register 0–1
Bit Enstuffing Circuit
PWM
Clock
Selection
LSB/MSB Selection
CRC unit
Bit Stuffing Circuit
Receive Output Buffer
(8bit)
Transmit Input Buffer
(8 bit)
Figure 9: Outline of Intelligent I/O Group 0
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In the following documentation, within some register names may “i” appear. This is a variable
for Intelligent I/O Group 0 and 1, because both Groups have similar registers and therefore
this documentation is transparent for both.
4.2.1 Basetimer clock generation
The clock for receive and transmit part is generated by the freerunning Basetimer, plus the
usage of two additional compare registers. Each unit, receive and transmit has their own
compare register.
• GiPO0 is the compare register for the Receive unit
• GiPO1 is the compare register for Transmit unit.
Is the value of the Basetimer equal to a compare register value, a logical high output will be
generated by the compare register. A rectangle clock is generated by this logic output and
feed to the appurtenant circuit. The following diagram should explain this function:
Match and
reset of
Basetimer
Freerunning
Basetimer
GiPO0
GiPO1
t
Output of
GiPO1
(Receive)
Output of
GiPO0
(Transmit)
2 cycle
t
tx
t
tx
Figure 10: Handling of Basetimer and Compare registers
Is the value of the Basetimer equal to the GiPO0 register value, the Basetimer will be reset
automatically (takes two cycles) and the clocks for receive and transmit block return into
logical low output state. Please make sure that the value of GiPO0 register is higher than the
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GiPO1 one. The shapes of the clocking signals are different from each other, but this doesn’t
matter, because only the rising edge is important for the following units and this frequency is
same for receive and transmit side. In this driver, basetimer frequency is set to around 1.6MHz
whereby fxin is 20MHz.
4.2.2 Receive HDLC unit
The receive unit is supplied with a clock which is generated by the output of the compare
register GiPO1.
The incoming HDLC data, which have been removed from GCI frame, should be written into
the receive input buffer (GiRI). From the receive buffer the data will be serial clocked to the
compare shift register (GiDR) and to the bit enstuffing unit.
The compare unit does a permanent comparison between current serial data stream and the
values inside the data compare registers. For the registers GiCMP0 and GiCMP1 an
additional mask register called GiMSK0 and GiMSK1 is available. If the current data matches
one of this compare registers, a trigger signal CMP0T-CMP3T will be released. This signal
can be used in the driver software for flag recognition, e.g. start/end flag or abort flag.
Therefore the recommended setting for the compare registers is:
• GiCMP0 = 0xFF and GiMSK0 = 0x7F used for abort detection
• GiCMP3 = 0x7E used for start/end flag detection
The other compare and mask register will not be used for standard HDLC processing.
The bit enstuffing unit scans the incoming serial data stream, for a sequence of five “1” binary.
If the next bit of such sequence is “0”, the bit is discarded and the frame continues. Meanwhile,
the enstuffing unit sends a stop signal to the clock wait unit. So, the deleted “0” bit is not
shifted anymore to the output buffer and CRC generation unit. Shortly after this deletion the
stop signal is withdrawn, so standard clocking take place again. If the bit after a sequence of
five “1s” is also “1” a start/end flag is been detected by the compare unit and the responsible
compare register outputs a trigger signal.
The enstuffed data stream is clocked to the CRC controller and to the receive shift register. If
the receive shift register is full, the data will be backup into the receive output register, where
the data can be read out by the software driver. During this, the CRC unit generates
permanent the CRC of the incoming data. If an end flag is detected by the compare unit, the
CRC will be moved into the receive CRC register, where the CRC can be read out. Due to
these circumstances the CRC generation stops working after end flag is detected, so the
complete end flag is also involved in the current generated CRC code. Because of this
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algorithm the generated CRC is for every received frame equal. That means don’t care what
kind of frame was received, the CRC is 0x0B9F hex, in case the frame was received without
error.
Clock generation by
Basetimer
Receive Input Buffer
GiRI
Bit
Enstuffing
Unit
Clock wait
unit
Compare Shift Register
GiDR
CMP0T
data bus
Data Compare Register GiCMP0
Data Compare Mask Register GiMSK0
CRC Controller
CMP1T
Data Compare Register GiCMP1
Receive CRC Register
GiRCRC
Receive Shift Register
Receive Output Buffer
GiRB
Data Compare Mask Register GiMSK1
Data Compare Register GiCMP2
Data Compare Register GiCMP3
CMP2T
CMP3T
Figure 11: Outline of Receive HDLC unit
4.2.3 Transmit HDLC unit
The transmit unit is supplied with a clock which is generated by the output of the compare
register GiPO0.
To transmit data using the HDLC block, the data have to be written into the transmit buffer
(GiTB). First of all a start flag should be written into this register, followed by the rest of the
HDLC frame. For transmission of the start flag, the bit stuffing unit and CRC unit should be
disabled. The data will be shifted, with help of transmit shift register to the bit stuffing unit. The
bit stuffing unit scans the incoming serial data stream, for a sequence of five “1s” binary. If
such data stream is detected, the bit stuffing unit stops clocking for the transmit shift register
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Software driver for M32C/83’s GCI and HDLC feature
and CRC controller, by using the clock wait unit. Therefore the bit stuffing unit is now able to
insert a zero bit into the data stream. Shortly after this insertion the stop signal is withdrawn,
so standard clocking take place again and the frame continues. The CRC unit generates
permanent the CRC of the incoming unstuffed data stream. Is the HDLC frame is completed
the CRC can be read out of the transmit CRC register (GiTCRC). Because the CRC itself has
to be stuffed, too. The CRC code has to be written into the transmit buffer. The stuffing unit
does the stuffing of the CRC, like it has done for the previous data and the result will be
available in the transmit output register (GiTO). To finalize the HDLC frame an end flag should
be attached by the transmit unit, whereby the stuffing unit and CRC controller are disabled
again.
Clock generation by
Basetimer
Transmit Buffer
GiTB
Transmit Shift Register
Bit
Stuffing
Unit
data bus
Clock wait
unit
CRC Controller
Transmit CRC Register
GiTCRC
Transmit Output Register
GiTO
Figure 12: Outline of Transmit HDLC unit
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4.3
HDLC Software Driver
This Software Driver supports two HDLC channels (HDLC0 and HDLC1 block of Intelligent I/O
group 0 and 1), depending on define pre-processor directive in the main.c file. The needed
initialization of the HDLC blocks will be done by execution of the SWD_HDLC0_Init() and/or
SWD_HDLC1_Init() function. Because the HDLC driver itself needs an environment for
operation, it is linked to the GCI driver to show the functionality.
In the Service_8KHZ() routine, a specific slot of the GCI downstream frame will be extracted
and transferred to the HDLC receive input register, processed and finally read out of the
receive output register of the HDLC block. For GCI upstream direction, user data will be input
to the transmit input buffer of the HDLC block, processed and read out of the HDLC transmit
output buffer register and inserted into the specific slot of the GCI upstream frame.
To generated this necessary routing following order of function calls should be followed in the
Service_8KHZ callback function:
1.
2.
3.
4.
5.
6.
SWD_HDLC0_RcvOut
SWD_HDLC0_RcvPoll
SWD_HDLC0_RcvIn
SWD_HDLC0_SndPoll
SWD_HDLC0_SndIn
SWD_HDLC0_SndOut
This is the order for the function calls for HDLC0 generation only. If HDLC1 is needed as well
please use the similar functions for the HDLC1 block afterwards. Furthermore, following two
paragraphs describe the HDLC0 block, but HDLC1 block, function and handling is similar.
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Intelligent I/O Group0
GCI Buffer for Receive
(+shadow buffer)
ucSWD_GCI_RcvBuffer
Byte 0
Byte1 0
Byte
Byte
1
.
.
.
. .
. .
. .
. .
. .
Byte. x
Byte x
HDLC0 block
G0RI
Receive
G0RB
Shift
Register
Enstuffing,
Flag, Abort
detection, CRC
Shift
Register
G0TO
Transmit
G0TB
Shift
Register
GCI Buffer for Transmit
(+shadow buffer)
ucSWD_GCI_SndBuffer
Byte 0
Byte1 0
Byte
Byte
1
.
.
.
. .
. .
. .
. .
. .
Byte. x
Byte x
Stuffing,
CRC
Shift
Register
Intelligent I/O Group1
HDLC1 block
G1RI
Receive
G1RB
Shift
Register
Enstuffing,
Flag, Abort
detection, CRC
Shift
Register
G1TO
Transmit
G1TB
Shift
Register
Stuffing,
CRC
Shift
Register
HDLC Buffer for Receive
ucHDLC0_RcvOut
Byte 0
Byte 1
.
.
Byte y
HDLC Buffer for Transmit
ucHDLC0_SndIn
Byte 0
Byte 1
.
.
Byte y
HDLC Buffer for Receive
ucHDLC1_RcvOut
Byte 0
Byte 1
.
.
Byte y
HDLC Buffer for Transmit
ucHDLC1_SndIn
Byte 0
Byte 1
.
.
Byte y
Figure 13: HDLC driver concept
4.3.1 Receive HDLC
The first step in the HDLC driver is to check, whether data is available in receive output buffer
G0RB. Therefore the function SWD_HDLC0_RcvOut() will executed and the data of the
output buffer register will be stored in the buffer array ucHDLC0_RcvOut. Additional the index
counter ulSWD_HDLC0_RcvIndex for the array access will be incremented. If this counter
exceeds the limit, it will be set to a fix value and an overflow counter will be incremented.
The next step is calling of SWD_HDLC0_RcvPoll() function. Within this routine the handling of
the compare registers of the HDLC receive block is done. If no interrupt request flag have
been set by the compare registers, the routine will be left without action, but if a start/end or
abort detection flag is set, a dummy read is done at the receive output register, the flag itself
and receive output buffer full interrupt request flag will be reset.
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In case start/end flag has been detected, abort detection will be enabled. The current amount
of received bytes will be compared with a minimum frame length parameter to determine,
whether flag is start or end flag. If the current frame length is smaller than the minimum length
value, the flag will be identified as start flag. If a start flag has been detected already in one of
the previous passes, the flag is identified as end flag. Now the CRC will be read out of
G0RCRC register and will be compared to the expected CRC.
In case an abort flag is detected, abort flag detection will be disabled until next start/end flag
will be detected and a possible previous recognized start flag and current frame as well would
be discarded.
Then the selected byte of the downstream GCI frame will be transferred to the
SWD_HDLC0_RcvIn() function as parameter, containing pointer to storage location of GCI
frame and a offset for the selected byte. Within SWD_HDLC0_RcvIn() function the received
byte is written into the receive input buffer of the HDLC0 block.
4.3.2 Transmit HDLC
First action for the transmit HDLC block treatment is to execute the SWD_HDLC0_SndPoll()
function. If a transmission has been started already with the SWD_HDLC0_SndIn() function, a
state machine procedure will start, to do the necessary settings for bit stuffing, CRC
generation and flag transmission, otherwise the function will be left without action.
The state machine consist of following states, which will be executed in the following order as
well:
State
SWD_HDLC_SND_STATE_DATA
SWD_HDLC_SND_STATE_CRCL
SWD_HDLC_SND_STATE_CRCH
SWD_HDLC_SND_STATE_FLAG
SWD_HDLC_SND_STATE_FILL
SWD_HDLC_SND_STATE_END
Purpose
Transmission of data and enabling of bit stuffing
Transmission of low byte of CRC
Transmission of high byte of CRC
Disable of bit stuffing and transmission of end flag
Transmission of fill byte
Final state
Table 3: States of SWD_HDLC0_SndPoll() function
In the first state the bit stuffing unit will be enabled and the data array, where
pucSWD_HDLC0_SndInput is pointing to, is transferred to the G0TB register. Additional this
data is input to the standard CRC circuit for transmit CRC generation. If the frame is complete
transferred to G0TB register, the generated CRC will be read out in the next state and also
transferred to the G0TB register, to process the bit stuffing. Afterwards the bit stuffing unit will
be disabled and an end flag is transferred to the G0TB register, followed by filling data to
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Software driver for M32C/83’s GCI and HDLC feature
assure that the end flag is completely clocked through the transmit HDLC block. Finally, the
final state disables the transmit block and reset all possible open requests as well as some
dummy read of G0TO.
Please note, that the usage of transmit HDLC block internal CRC generation circuit is not
recommended, if no interrupt routine is used for HDLC handling. Therefore, this driver utilized
the standard CRC generation circuit of the M32C/83 for transmit CRC generation.
The SWD_HDLC0_SndIn() function call, includes a pointer and a length variable as
parameter for indication of next transmit HDLC frame. As long as the return value of this
function is ERROR, you should not change the selected HDLC frame. If the return value is OK
the selected frame is already on transmission and a new frame can be selected for next
transmission procedure. The transmit HDLC block is enabled, the transmit state machine is
set to SWD_HDLC_SND_STATE_DATA and index variables are set to zero. Then the routine
writes the start flag into the G0TB register, which actually starts the complete transmission.
Then the address of the selected byte for the upstream GCI frame will be transferred to the
SWD_HDLC0_SndOut() function as parameter, containing pointer to storage location of GCI
frame and a offset for the selected byte. Within SWD_HDLC0_SndOut() function a byte will be
written into the specific slot of the GCI frame. In case no byte is available at the transmit output
buffer register G0TO, the software supposes that currently no HDLC frame has to be
transmitted and instead of that a SWD_HDLC0_PAUSE byte is inserted to the GCI frame,
which could be mark idle or flag idle data bytes. This can be selected by the user, via
pre-processor directive in the local header part of the SWD_HDLC0.c and SWD_HDLC1.c
file.
4.4
HDLC Software Driver Flow diagram
The described Software Driver for HDLC purpose is written in C-Source.
The HDLC driver consists of SWD_HDLC0.c, SWD_HDLC1.c, SWD_HDLC0.h and
SWD_HDLC1.h file. In the user code the SWD_HDLC0_Init() and SWD_HDLC1_Init()
functions have to be called. Additional, some action have to been done in a polling style. To
combine GCI and HDLC functionality, it is recommended to use the Service_8KHZ function to
handle these items.
The driver handles Intelligent I/O Group 0 and 1, anyway the flow diagram just for the HDLC0
group usage are attached, because flow diagram for HDLC1 is quite similar.
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The following function will be used:
Functionname
Main()
Service_8KHZ()
SWD_HDLC0_Basetimer_Init()
SWD_HDLC0_Init()
SWD_HDLC0_RcvIn()
SWD_HDLC0_RcvOut()
SWD_HDLC0_RcvPoll()
SWD_HDLC0_SndIn()
SWD_HDLC0_SndOut()
SWD_HDLC0_SndPoll()
SWD_HDLC1_Basetimer_Init()
SWD_HDLC1_Init()
SWD_HDLC1_RcvIn()
SWD_HDLC1_RcvOut()
SWD_HDLC1_RcvPoll()
SWD_HDLC1_SndIn()
SWD_HDLC1_SndOut()
SWD_HDLC1_SndPoll()
Purpose
Main routine
Interrupt Callback function of user
Initialization of HDLC0 basetimer
Initialization of HDLC0 block in general
Handling of data input for receive HDLC0 block
Handling of data output for receive HDLC0 block
HDLC0 polling routine for receive communication
HDLC0 transmit start function
Handling of data output for transmit HDLC0 block
HDLC0 polling routine for transmit communication
Initialization of HDLC1 basetimer
Initialization of HDLC1 block in general
Handling of data input for receive HDLC1 block
Handling of data output for receive HDLC1 block
HDLC1 polling routine for receive communication
HDLC1 transmit start function
Handling of data output for transmit HDLC1 block
HDLC1 polling routine for transmit communication
Table 4: Functions of the HDLC software driver
4.4.1 Main() function
Start
Function: main()
SWD_HDLC0_Init()
SWD_GCI_Init
(SERVICE_8KHZ)
__enable_interrupt()
SWD_GCI_Start()
while(1)
Yes
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4.4.2 Service_8KHZ() function
Start
Function: Service_8KHZ()
Parameter: pucTransmit
pucReceive
Set ucHDLC0_SlotNumber to a
selected slot number
SWD_HDLC0_RcvOut()
SWD_HDLC0_RcvPoll()
SWD_HDLC0_RcvIn() with
pucReceive and
ucHDLC0_SlotNumber as parameter
SWD_HDLC0_SndPoll()
SWD_HDLC0_SndIn() with
&ucHDLC0_SndIn[FIRST_DATA_INDEX],
ucHDLC0_SndIn[LENGTH_PARAMETER])
as parameter
SWD_HDLC0_SndOut() with
pucTransmit and
ucHDLC0_SlotNumber as parameter
End
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4.4.3 SWD_HDLC0_Basetimer_Init() function
Function: SWD_HDLC0_Basetimer_Init()
Start
Select f1 as clock source, without
prescaler for basetimer 2 @ G2BCR0
register
Reset basetimer 0 start flag @ BTSR
register
Select f1 as clock source, without
prescaler for basetimer 0 @ G0BCR0
register
Select basetimer reset, if basetimer
value matches WG Ch0 register @
G0BCR1 register
Set waveform generation register0 to
single PWM mode @ G0POCR0
Set waveform generation register1 to
single PWM mode @ G0POCR1
Set waveform generation register 0
to fix value e.g. 0x10 @ G0PO0
register
Set waveform generation register 1
to fix value (half of G0PO0) @
G0PO1 register
Enable channel 0 and 1 waveform
registers @ G0FE
Start basetimer 0 @ DRC0 register
End
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4.4.4 SWD_HDLC0_Init()
Function: SWD_HDLC0_Init()
Start
SWD_HDLC0_Basetimer_Init()
Select HDLC as special
communication mode for HDLC0 @
G0MR register
Disable transmit and receive HDLC0
@ G0CR register
Enable receive HDLC0 @ G0CR
register
Enable flag detection, bit enstuffing,
receive CRC and receive switch @
G0ERC register
Set HDLC0 compare and mask
registers @ G0CMP0, G0MSK0 and
G0CMP3 register
Disable transmit CRC and bit stuffing
@ G0ETC register
Set interrupt priority levels for
Intelligent I/O Group0 to "zero" @
IIO0IC, IIO1IC and IIO4IC register
Enable auto CRC init, select 0xFFFF
as CRC init, select parallel output,
CRC polynom @ G0EMR register
Write dummy data to receive input
buffer @ G0RI register
Yes
if G0BT >= 0x0010
No
Select parallel input @ G0EMR
register
Initialization of all error and event
counter with ZERO
Initialization of messages
msgSWD_HDLC0.TransmitStart and
msgSWD_HDLC0.ReceiveFlagDetected with
NO
Initialization of received HDLC data
index ulSWD_HDLC0_RcvIndex with
ZERO
End
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4.4.5 SWD_HDLC0_RcvIn() function
Function: SWD_HDLC0_RcvIn()
Parameter: pucRcvIn
ucSlot
Start
Check interrupt
request bit for receive input
buffer empty @ IIO0IR
No
Yes
Reset interrupt request flag bit for
receive input buffer empty @ IIO0IR
register
Increment
ulSWD_HDLC0_CntRcvG0RI_NotEmpty
Read GCI downstream buffer, with the help
of pucRcvIn pointer and ucSlot as index and
write into receice input buffer @ G0RI
End
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4.4.6 SWD_HDLC0_RcvOut() function
Function: SWD_HDLC0_RcvOut()
Start
No
Check interrupt
request bit for receive output
buffer full @ IIO0IR
Yes
Reset interrupt request flag bit for
receive output buffer full @ IIO0IR
register
Store receive output buffer in
ucHDLC0_RcvOut array, by using
ulSWD_HDLC0_RcvIndex @ G0RB register
Increment ulSWD_HDLC0_RcvIndex
ulSWD_HDLC0_RcvIndex
>= BUFFER_SIZE-1
No
Yes
Set ulSWD_HDLC0_RcvIndex to
BUFFER_SIZE-1
Increment
ulSWD_HDLC0_CntRcvBufferOverRun
End
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4.4.7 SWD_HDLC0_RcvPoll() function
Start
Function: SWD_HDLC0_RcvPoll()
Check
interrupt request bit,
Flag detect?
@ G0IRF
Check
interrupt request bit,
abort detect?
@ G0IRF
No
Yes
Yes
Dummy read of receive output buffer
@ G0RB register
Dummy read of receive output buffer
@ G0RB register
Reset interrupt request for receive
output buffer full @ IIO0IR register
Reset interrupt request for receive
output buffer full @ IIO0IR register
Reset interrupt request flag for start
or end flag detection @ G0IRF
register
Reset interrupt request flag for abort
flag detection @ G0IRF register
Enable abort and flag detection, bit
enstuffing, receive CRC and receive
switch @ G0ERC register
ulSWD_HDLC0_RcvIndex <
SWD_HDLC0_FRAME_MIN?
Yes
Set ulSWD_HDLC0RcvIndex to
ZERO
Increment counter
ulSWD_HDLC0_CntRcvFrameShort
msgSWD_HDLC0.ReceiveFlagDetec
ted = YES
No
Disable abort
detection, bit enstuffing, receive
CRC and receive switch @ G0ERC
register
No
No
msgSWD_HDLC0.ReceiveFlag
Detected = NO?
Yes
msgSWD_HDLC0.ReceiveFlagDetec
ted = YES
msgSWD_HDLC0.ReceiveFlagDetec
ted = NO
msgSWD_HDLC0.ReceiveFlag
Detected = YES?
Yes
Set ulSWD_HDLC0RcvIndex to
ZERO
Read low byte of CRC @ G0RCRCL
Increment counter
ulSWD_HDLC0_CntRcvAbortError
Read high byte of CRC @
G0RCRCH
Is generated CRC wrong?
No
Yes
Set ulSWD_HDLC0RcvIndex to
ZERO
Set ulSWD_HDLC0RcvIndex to
ZERO
Increment counter
ulSWD_HDLC0_CntRcvCRCError
Increment counter
ulSWD_HDLC0_CntRcvCRCFrameOK
End
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4.4.8 SWD_HDLC0_SndIn() function
Function: SWD_HDLC0_SndIn()
Parameter: pucSndInput
usLength_SndInput
Return: unsigned char
Start
Yes
msgSWD_HDLC0.TransmitStart
= YES?
No
Set msgSWD_HDLC0.TransmitStart
= YES
exit SWD_HDLC0_SndIn() function
and return ERROR as feedback
Enable transmit HDLC0 @ G0CR
register
End
Set pointer
pucSWD_HDLC0_SndInput to
pucSndInput
Set ucSWD_HDLC0SndState to
SWD_HDLC_SND_STATE_DATA
Set ucSWD_HDLC0SndIndex to
ZERO
Set ucSWD_HDLC0SndLength to
usLength_SndInput
Write start flag to transmit input
buffer @ G0TB register
Set CRC_HDLC0_Snd.word to
ZERO
Increment
ulSWD_HDLC0_CntSndFrameStarted
exit SWD_HDLC0_SndIn() function
and return OK as feedback
End
REB05B0007-0101Z
May 2003
Page 33 of 74
M16C Family
Software driver for M32C/83’s GCI and HDLC feature
4.4.9 SWD_HDLC0_SndOut() function
Function: SWD_HDLC0_SndOut()
Parameter: pucSndOut
ucSlot
Start
Check interrupt
request bit for transmit output
buffer full @ IIO1IR
No
Reset interrupt request flag bit for
transmit output buffer full @ IIO1IR
register
Write transmit output buffer into the GCI
upstream buffer, with the help of pucSndOut
pointer and ucSlot as index @ G0TO register
Yes
Write SWD_HDLC0_PAUSE data into the
GCI upstream buffer, with the help of
pucTransmit pointer and
ucHDLC0_SlotNumber as index @ G0TO
register
Increment
ulSWD_HDLC0_CntG0TO_NotReady
End
REB05B0007-0101Z
May 2003
Page 34 of 74
M16C Family
Software driver for M32C/83’s GCI and HDLC feature
4.4.10 SWD_HDLC0_SndPoll() function
Function: SWD_HDLC0_SndPoll()
Start
Check
interrupt request bit
for tranmit input buffer empty?
@ IIO1IR
No
Yes
Reset interrupt request for transmit
input buffer empty @ IIO1IR register
No
msgSWD_HDLC0.TransmitStart
= YES?
Yes
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ulSWD_HDLC0_CntSndG0TB_NotR
eady
ucSWD_HDLC0_SndState
SWD_HDLC_SND_STATE_DATA
SWD_HDLC_SND_STATE_CRCL
SWD_HDLC_SND_STATE_CRCH
Invert value inside
CRC_HDLC0_Snd.word
SWD_HDLC_SND_STATE_FLAG
SWD_HDLC_SND_STATE_FILL
Write low CRC byte into Tranmsit
input buffer @ G0TB register
SWD_HDLC_SND_STATE_END
ucSWD_HDLC0_SndState =
SWD_HDLC_SND_STATE_CRCH
Change interrupt request to transmit
shift register empty @ G0MR register
Default
Write fill data into Tranmsit input
buffer @ G0TB register
Write high CRC byte into Tranmsit
input buffer @ G0TB register
Enable bit stuffing @ G0ETC register
ucSWD_HDLC0_SndState =
SWD_HDLC_SND_STATE_END
ucSWD_HDLC0_SndState =
SWD_HDLC_SND_STATE_FLAG
pucSWD_HDLC0_SndInput +
usSWD_HDLC0_SndIndex to Tranmsit input
buffer @ G0TB register
Change interrupt request to transmit
buffer empty @ G0MR register
Disable bit stuffing @ G0ETC
register
Set standard CRC register to
CRC_HDLC0_Snd.word @ CRCD
register
Disable transmit HDLC0 @ G0CR
register
Write end flag into Transmit input
buffer @ G0TB register
Set standard CRC input buffer =
pucSWD_HDLC0_SndInput +
usSWD_HDLC0_SndIndex @ CRCIN
Reset interrupt request for transmit
input and output @ IIO1IR register
ucSWD_HDLC0_SndState =
SWD_HDLC_SND_STATE_FILL
wait for two cycles:
two NOP instruction
Dummy read of transmit output buffer
@ G0TO register
Read standard CRC register and store value
at CRC_HDLC0_Snd.word @ CRCD register
msgSWD_HDLC0.TransmitStart =
NO
Increment ulSWD_HDLC0_SndIndex
Increment
ulSWD_HDLC0_CntSndFrameOK
ulSWD_HDLC0_SndIndex >=
usSWD_HDLC0_SndLength?
ucSWD_HDLC0_SndState =
SWD_HDLC_SND_STATE_END
ucSWD_HDLC0_SndState =
SWD_HDLC_SND_STATE_CRCL
End
REB05B0007-0101Z
May 2003
Page 35 of 74
M16C Family
Software driver for M32C/83’s GCI and HDLC feature
5 GCI-HDLC Driver C source code
This C source code supports IAR and Renesas compiler. To get a complete working project, a
SFR header file and the related Cstartup files have to be added to these files to get a running
project.
5.1
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REB05B0007-0101Z
May 2003
Page 38 of 74
M16C Family
Software driver for M32C/83’s GCI and HDLC feature
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REB05B0007-0101Z
May 2003
Page 39 of 74
M16C Family
Software driver for M32C/83’s GCI and HDLC feature
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Page 40 of 74
M16C Family
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M16C Family
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May 2003
Page 72 of 74
M16C Family
Software driver for M32C/83’s GCI and HDLC feature
6 Reference
Renesas Technology Corporation Semiconductor Home Page
http://www.renesas.com
Contact for Renesas Technical Support
E-mail: [email protected]
Data Sheet & User’s Manual
M32C/83 Datasheet, User’s Manual
(Use the latest version, please check: http://www.renesas.com)
REB05B0007-0101Z
May 2003
Page 73 of 74
M16C Family
Software driver for M32C/83’s GCI and HDLC feature
Keep safety first in your circuit designs!
• Renesas Technology Corporation puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with them.
Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
• These materials are intended as a reference to assist our customers in the selection of the
•
•
•
•
•
•
•
Renesas Technology Corporation product best suited to the customer'
s application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Renesas Technology Corporation or a third party.
Renesas Technology Corporation assumes no responsibility for any damage, or infringement of
any third-party'
s rights, originating in the use of any product data, diagrams, charts, programs,
algorithms, or circuit application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs
and algorithms represents information on products at the time of publication of these materials,
and are subject to change by Renesas Technology Corporation without notice due to product
improvements or other reasons. It is therefore recommended that customers contact Renesas
Technology Corporation or an authorized Renesas Technology Corporation product distributor
for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by
various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products.
Renesas Technology Corporation assumes no responsibility for any damage, liability or other
loss resulting from the information contained herein.
Renesas Technology Corporation semiconductors are not designed or manufactured for use in a
device or system that is used under circumstances in which human life is potentially at stake.
Please contact Renesas Technology Corporation or an authorized Renesas Technology
Corporation product distributor when considering the use of a product contained herein for any
specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
The prior written approval of Renesas Technology Corporation is necessary to reprint or
reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they
must be exported under a license from the Japanese government and cannot be imported into a
country other than the approved destination. Any diversion or reexport contrary to the export
control laws and regulations of Japan and/or the country of destination is prohibited.
Please contact Renesas Technology Corporation for further details on these materials or the
products contained therein.
REB05B0007-0101Z
May 2003
Page 74 of 74
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