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INDEX
instruction ordering instructions, 5-15, 5-18
I/O instructions, 5-6, 7-20
logical instructions, 7-10
MMX instructions, 5-10, 9-5
multiply and divide instructions, 7-9
processor identification instruction, 7-23
repeating string operations, 7-19
rotate instructions, 7-13
segment register instructions, 7-22
shift instructions, 7-10
SIMD instructions, introduction to, 2-14
software interrupt instructions, 7-17
SSE instructions, 5-12
SSE2 instructions, 5-15
stack manipulation instructions, 7-5
string operation instructions, 7-18
summary, 5-1
system instructions, 5-26
test instruction, 7-14
type conversion instructions, 7-7
x87 FPU and SIMD state management instructions, 5-10
x87 FPU instructions, 5-7
INT instruction, 6-12, 7-23
Integers
description of, 4-3
indefinite, 4-4, 8-13
signed integer encodings, 4-4
signed, description of, 4-4
unsigned integer encodings, 4-3
unsigned, description of, 4-3
Intel 64 architecture
64-bit mode, 3-1
64-bit mode instructions, 5-27
address space, 3-6
compatibility mode, 3-1
data types, 4-1
definition of, 1-3
executing calls, 6-1
general purpose instructions, 7-1
generations, 2-20
history of, 2-1
IA32e mode, 3-1
introduction, 2-20
memory organization, 3-6, 3-7
relation to IA-32, 1-3
See also: IA-32e mode
Intel Advanced Digital Media Boost, 2-4, 2-10
Intel Advanced Smart Cache, 2-10
Intel Advanced Thermal Manager, 2-4
Intel Core 2 Extreme processor family, 2-4, 2-5, 2-18
Intel Core Duo processor, 2-4, 2-17
Intel Core microarchitecture, 2-4, 2-5, 2-10, 2-12, 2-13, 2-18
Intel Core Solo processor, 2-4
Intel developer link, 1-7
Intel Dynamic Power Coordination, 2-4
Intel NetBurst microarchitecture, 1-2
description of, 2-8
introduction, 2-8
Intel Pentium D processor, 2-17
Intel Pentium processor Extreme Edition, 2-17
Intel Smart Cache, 2-4
Intel Smart Memory Access, 2-4, 2-10
Intel software network link, 1-7
Intel VTune Performance Analyzer
related information, 1-7
Intel Wide Dynamic Execution, 2-4, 2-10, 2-12, 2-13
Intel Xeon processor, 1-1
description of, 2-3
Intel Xeon processor 5100 series, 2-4, 2-5, 2-18
Intel386 processor, 2-1
Intel486 processor
history of, 2-2
INDEX-6 Vol. 1
Inter-privilege level call
description of, 6-6
operation, 6-7
Inter-privilege level return
description of, 6-6
operation, 6-7
Interrupt gate, 6-9
Interrupt handler, 6-9
Interrupt vector, 6-9
Interrupts
64-bit mode, 6-13
description of, 6-9
handler, 6-9
implicit call to an interrupt handler
procedure, 6-9
implicit call to an interrupt handler task, 6-12
implicit call to interrupt handler procedure, 6-9
implicit call to interrupt handler task, 6-12
in real-address mode, 6-12
maskable, 6-9
user-defined, 6-9
vector, 6-9
INTn instruction, 7-17
INTO instruction, 6-12, 7-18, 7-23
Invalid arithmetic operand exception (#IA)
description of, 8-26
masked response to, 8-26
Invalid operation exception (#I)
overview, 4-20
SSE and SSE2 extensions, 11-14
x87 FPU, 8-25
IOPL (I/O privilege level) field
EFLAGS register, 3-16, 14-3
IRET instruction, 3-17, 6-11, 6-12, 7-15, 7-23, 14-4
I/O
address space, 14-1
instruction serialization, 14-5
instructions, 5-6, 7-20, 14-3
I/O privilege level (see IOPL)
map base, 14-4
permission bit map, 14-4
ports, 3-3, 14-1, 14-2, 14-3, 14-5
sensitive instructions, 14-3
J
J-bit, 4-11
Jcc instructions, 3-16, 3-17, 7-15
JMP instruction, 3-17, 7-15, 7-22
L
L1 (level 1) cache, 2-7, 2-9
L2 (level 2) cache, 2-7, 2-9
LAHF instruction, 3-14, 7-21
Last instruction opcode, x87 FPU, 8-10
LDDQU instruction, 5-19, 12-3
LDMXCSR instruction, 10-12, 11-23
LDS instruction, 7-23
LDTR register, 3-4, 3-5
LEA instruction, 7-23
LEAVE instruction, 6-13, 6-18, 7-21
LES instruction, 7-23
LFENCE instruction, 11-12
LGS instruction, 7-23
Linear address, 3-6
Linear address space
defined, 3-6
maximum size, 3-6
LOCK signal, 7-4
LODS instruction, 3-16, 7-18
Log epsilon, x87 FPU operation, 8-21