Download MC68PM302 Integrated Multiprotocol Processor with PCMCIA

Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
D
DACK 6-24
DAPR 3-13
Default System Clock Generation 2-7
DF0–3 2-9
Disable CPU 6-7
BG 3-28
BR 3-28
CS0 3-28
DTACK 3-29
EMWS 3-29
SAM 3-29
Disable CPU Logic 3-28
DISC 4-2
DISCPU 3-28, 6-7
Divide by Two Block
From Tin1 Pin 4-3
DMA Control 3-11
DONE 6-25
DOZE 2-13, 2-15
DRAM Refresh
Buffer Descriptors 3-30
PB8 3-19
DREQ 6-24
DSR 4-4
DTACK 3-4, 3-5, 3-26, 3-29, 6-17, 6-31
Dynamic RAM Refresh Controller 3-30
Index
Freeze Control 3-6
Function Codes 3-14, 6-16, 6-32
Comparison 2-4
FC2-FC0 2-4, 6-16
Register 3-14
G
GCI 4-2, 6-18, 6-19
GCI See Signals
GIMR 3-15
GNDSYN 2-12
H
HALT 2-3, 6-10, 6-27
HALT See Signals
Hardware Watchdog 3-6
BERR 3-6
HDLC
HDLC Memory Map 4-18
HDLC Controller 4-18
HDLC Event Register 4-20
HDLC Mask Register 4-20
HDLC Mode Register 4-19
HDLC Receive Buffer Descriptor 4-19
HDLC Transmit Buffer Descriptor 4-19
Tx BD 4-19
HDLC Receive Buffer Descriptor 4-19
E
I
EMR 4-36
Emulation Controller 4-23
EMWS (External Master Wait State) 3-5, 329
Enable Receive 4-4
Enable Transmitter 4-4
Exception
PB8 3-30
EXTAL 6-6, 6-8
External
Bus Master 3-30
Master Wait State (EMWS) 3-5
External Bus Arbitration Using HALT 3-30
External Master Wait State 3-5
IACK or PIO Port B Pins 6-25
IACK7 6-25, 6-26
IDL 4-2, 6-18, 6-19
IDL See Signals
IDMA (Independent DMA Controller) 6-14, 624
DONE 3-12, 3-14
DREQ 3-12
IDMA or Port A Pins or PCMCIA Pins 6-24
IER 4-31
IIR 4-30
IMP Address and Function Codes or
PCMCIA Data 6-32
IMP Bus Control Pins 6-30
IMP Data Bus Pins 6-12
IMP Features
CP 1-2, 1-3
IMP Operation Mode Control Register
F
FCR 3-14, 4-29
MC68PM302 REFERENCE MANUAL
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