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Definition: UART Line Control Register Middle. Bit Descriptions: RSVD: Reserved. Unknown During Read. BR: Baud Rate Divisor bits [15:8]. Most significant byte of baud rate divisor. These bits are cleared to 0 on reset. UART2LinCtrlLow 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RSVD 15 14 13 12 11 10 9 8 RSVD BR Address: 0x808D_0010 - Read/Write Default: 0x0000_0000 Definition: UART Line Control Register Low. Bit Descriptions: RSVD: Reserved. Unknown During Read. BR: Baud Rate Divisor bits [7:0]. Least significant byte of baud rate divisor. These bits are cleared to 0 on reset. The baud rate divisor is calculated as follows: Baud rate divisor BAUDDIV = (F UARTCLK / (16 * Baud rate)) –1 where F UARTCLK is the UART reference clock frequency. A baud rate divisor of zero is not allowed and will result in no data transfer. EP9312 User’s Manual - DS515UM2 Copyright 2004 Cirrus Logic 521 NQ Q UART2 14
