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Download S1D13705F00A Technical Manual HARDWARE FUNCTIONAL
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7: A.C. CHARACTERISTICS 7.1.5 Generic #1 Interface Timing TBCLK BCLK A[16:0] VALID CS# t2 t1 WE0#,WE1# RD0#, RD1# t3 D[15:0] (write) t5 Hi-Z VALID t4 D[15:0] (read) Hi-Z VALID t9 t8 WAIT# t7 t6 Hi-Z t10 Hi-Z Hi-Z t11 Figure 7-5 Generic #1 Timing Symbol fBCLK TBCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Table 7-5 Generic #1 Timing Parameter Bus Clock frequency Bus Clock period A[16:0], CS# valid to WE0#, WE1# low (write cycle) or RD0#, RD1# low (read cycle) WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to A[16:0], CS# invalid WE0#, WE1# low to D[15:0] valid (write cycle) RD0#, RD1# low to D[15:0] driven (read cycle) WE0#, WE1# high to D[15:0] invalid (write cycle) D[15:0] valid to WAIT# high (read cycle) RD0#, RD1# high to D[15:0] high impedance (read cycle) WE0#, WE1# low (write cycle) or RD0#, RD1# low (read cycle) to WAIT# driven low BCLK to WAIT# high WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to WAIT# high impedance WAIT# high to WE0#, WE1#, RD0#, RD1# high Min. Max. 50 1/fBCLK Units MHz MHz 0 ns 0 ns TBCLK 17 10 ns ns ns ns 16 ns 16 ns 16 ns 0 0 1 TBCLK Note: CKIO may be turned off (held low) between accesses - see Section 13.5 “Turning Off BCLK Between Accesses” on page 1-70. 1-22 EPSON S1D13705F00A HARDWARE FUNCTIONAL SPECIFICATION (X27A-A-001-06)
