Download DSC56800EX Quick Start User Guide

/* on new devices, some external pins may be needed if PLLCR.PRESC=1 */
#if (defined(OCCS_VERSION_6) || defined(OCCS_VERSION_7)) &&
(defined(SIM_VERSION_7)||defined(SIM_VERSION_8)) && (OCCS_PLLCR_INIT & 0x4)
/* first get EXT_SEL and CLK_MODE values (see OSCTL register) */
#ifdef OCCS_OSCTL1_INIT
#define _OCCS_EXTSEL (((OCCS_OSCTL1_INIT) >> 10) & 0x1)
#define _OCCS_CLKMODE (((OCCS_OSCTL1_INIT) >> 12) & 0x1)
#else
#define _OCCS_EXTSEL 1 /* reset value is 1 */
#define _OCCS_CLKMODE 1 /* reset value is 1 */
#endif
#ifdef SIM_MISC0_INIT
#define _SIM_CLK1 (((SIM_MISC0_INIT) >> 1) & 0x1)
#else
#define _SIM_CLK1 0
#endif
//todo optimalise, check correct functionality (test all cases - CLKIN/EXTAL/CRYSTAL)
/* external clock on CLKIN (GPIO_C0) */
// EXTAL for black GPIOC1, XTAL=C0, EXTAL
for black GPIOC0, XTAL=C1
#if _OCCS_EXTSEL == 1
/* enable clock for GPIO_C*/
bfset 0x0010, ArchIO.Sim.sim_pce0
//enable CLKIN_0 or CLKIN_1
#if _SIM_CLK1
bfset 0x0002, ArchIO.Sim.sim_misc0
bfset 0x00C0, ArchIO.Sim.sim_gpscl
bfset 0x0008, ArchIO.PortC.per
#else
bfset 0x0001, ArchIO.Sim.sim_gpscl
bfset 0x0001, ArchIO.PortC.per
bfclr 0x0002, ArchIO.Sim.sim_misc0
#endif
/* external clock on XTAL (GPIO_C0)*/
#else
/* enable clock for GPIO_C*/
bfset 0x0010, ArchIO.Sim.sim_pce0
bfclr 0x0001, ArchIO.Sim.sim_gpscl
bfset 0x0001, ArchIO.PortC.per
/* crystal on EXTAL and XTAL pins (GPIO_C1 and GPIO_C0)*/
#if _OCCS_CLKMODE == 0
bfset 0x0002, ArchIO.PortC.per
/* give it some time until crystal/resonator stabilizes */
/* we now run from internal relaxation oscillator / 2 (i.e. 4MHz) */
move.w #5000,x0
/* wait 50ms */
do x0,waitosc
rep 36; nop;
/* sigle loop pass takes 40 cycles */
move.w C1,X:(R5) /* and also clears the watchdog */
move.w D1,X:(R5)
waitosc:
DSC56800EX Quick Start User’s Guide, Rev. 2, 04/2015
Freescale Semiconductor, Inc.
2-51