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Transcript
S3C825A/P825A CONTROL REGISTER ADCON — A/D Converter Control Register EFH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – 0 0 0 0 0 0 Read/Write – – R/W R/W R R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 Not used for the S3C825A .5–.4 A/D Input Pin Selection Bits .3 .2–.1 .0 0 0 AD0 (P3.0) 0 1 AD1 (P3.1) 1 0 AD2 (P3.2) 1 1 AD3 (P3.3) End-of-Conversion Bit (read-only) 0 Conversion not complete 1 Conversion complete Clock Source Selection Bits 0 0 fxx/16 0 1 fxx/8 1 0 fxx/4 1 1 fxx Start or Enable Bit 0 Disable operation 1 Start operation (automatically disable operation after conversion complete). 4-5
