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Download UG638 - Xilinx
Transcript
To FIFO Parameters used by this block are explained in the topic Common Options in Block Parameter Dialog Boxes. Xilinx LogiCORE This block is implemented with the Xilinx LogiCORE™ FIFO Generator: System Generator Block To FIFO LogiCORE Xilinx ™ Version / LogiCORE ™ Data Sheet 3,3E FIFO Generator V5.3 • Spartan® Device Virtex® Device 3A 3A DSP 6 6 -1L 4 5 5Q 6 6 -1L • • • • • • • • • See Also The following topics provide valuable insight into using and understanding the From FIFO block: From FIFO, Multiple Subsystem Generator, Co-Simulating Shared FIFOs System Generator for DSP Reference Guide UG638 (v11.4) December 2, 2009 www.xilinx.com 339
