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1. Compaction of the generated code is optional. The compaction phase can be switched off to simplify subsequent fault
localization. If many instructions are executed in parallel, it
could be more difficult to localize a fault.
2. Generation of external stimuli is possible, because the code
generator must be able to allocate constants for all signals
including primary inputs.
3. To deal with different hardware realizations for conditional
jumps and comparison operations, a concurrent application
of transformation rules during resource allocation is performed (i.e. code selection and resource allocation are coupled).
4. In order to allocate constants efficiently, potential constant
sources and the paths from these sources to certain destinations are precomputed in a circuit analysis phase.
The remaining part of the paper is organized as follows: Section 4 describes the inputs of the system: hardware and test
specification. Section 5 contains the detailed description of the
retargetable code generation process. Section 6 shows the
experimental results followed by the conclusions.
4. INPUT SPECIFICATION: HARDWARE AND SOFTWARE
4.1 PROCESSOR DESCRIPTION
For the specification of the target processor we use structural
models. Datapath and controller must be completely described
with MIMOLA or VHDL. Hardware descriptions must contain
RT modules, their behavior and their interconnections. From
this we generate an intermediate tree based format, representing the target structure as a netlist of RT modules and the
behavior of every RT module as a tree (Fig. 5).
4.2 SELF-TEST PROGRAM SPECIFICATION
TCL is an imperative language in which the following kinds of
test statements are allowed to specify a self-test program (#
precedes a hexadecimal number; % precedes a binary number;
a variable location is referred to by <ComponentName>/<VariableName>):
•An Initialization causes the compiler to produce code for
loading a register or one cell of a memory with a constant initialization value.
Examples: RAM/cells[0] := #FF; REGISTER/store := 17;
•A Read Test makes the compiler produce code for testing if
a memory cell or a register contains a certain value.
Examples: TEST RAM/cells[0] = #FF;
TEST REGISTER/store = 17;
•An Initialization and Read Test combines an initialization
with a read test, i.e. the generated code first loads the specified
location with a value and then checks if it really contains that
value.
Examples: TEST RAM/cells[0] := #FF;
TEST REGISTER/store := 17;
•A Component Test makes the compiler produce code for
testing the functionality of any module, i.e. the related module’s input ports are stimulated with the specified values, and
then the outputs are checked for correctness. The programmer
needs only to specify the input values which should be hierarchically generated by a test pattern generator. An integrated
structure simulator calculates the corresponding output values.
An underscore may be used to denote a port of the module
which is not relevant to the test whereas X denotes a binary
don’t care.
Example: TEST ALU(%00,_, #FF);
•A Loop is used to apply one of the first four kinds of statements several times with one argument iterating over a range
of values. Examples:
FOR adr := 0 TO 15 DO RAM/cells[adr] := adr;
FOR adr := 3 TO 10 DO TEST RAM/cells[adr] = #A;
FOR i := 3 TO 10 DO TEST RAM/cells[i] := #A;
FOR i := 0 TO 3 DO TEST ALU(i, #FF, #AA);
The meaning of the keyword TEST is the following:
RESTART is directed to generate code that checks if the output
ports of a certain component are as expected. Therefore a conditional jump is generated:
IF component answer = expected answer
THEN increment program counter ELSE jump to error label;
If no error occurs, the program continues with the execution of
the next instruction of the self-test program, otherwise a jump
to an error procedure is performed. TCL allows the specification of all kinds of tests including memory test loops.
5. RETARGETABLE COMPILATION OF SELF-TEST PROGRAMS
We briefly discuss the circuit analysis phase (Fig. 1) followed
by the main part of the work: retargetable compilation of selftest programs.
5.1 CIRCUIT ANALYSIS
In the circuit analysis phase the given processor is analysed
and a subset of the instruction set is extracted. The result is a
list of microoperations the processor can perform and contains
e.g. the following operations: register transfer moves, conditional and unconditional jumps, counter increment operations,
etc. The considered subset is powerful enough to deal with the
compilation of TCL programs as described above.
5.2 RETARGETABLE CODE GENERATION
Fig. 2 shows the program flow of the retargetable compiler. A
hardware description, the output of the circuit analysis phase
and the TCL program serve as inputs. The code generation
phase described in the next subsection computes a relocatable
program. With respect to a certain program counter initialization value, the relocatable program has to be scheduled and
linked to a designated program start address. RESTART is able
to compact the generated code optionally, in order to allow a)
detailed analyses of the hardware and b) subsequent fault local-