Download DPhyDecoderHSCtl User`s Manual

The Moving Pixel Company DPhyDecoderHSCtl User’s Manual. – Rev. 1.1 -- 6/25/15
1 Overview
The Moving Pixel Company DPhy Decoder HS is an instrument designed to monitor and
decode traffic on up to 4 MIPI DPhy lanes running up to 2.5 Gbps. The instrument
operates as stand-alone acquisition hardware for DPhy bus activity, and is used in
conjunction with controlling software that also provides DSI, CSI-2, and DPhy protocol
decode of acquired data.
The main functions of the DPhy Decoder HS hardware are to:
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Input and convert serial HS packet data to bytes
Input and convert encoded LPDT and escape mode data to bytes
Process DPhy data and package into records
Provide DPhy, DSI, and CSI-2 protocol and state triggering for acquisition
Store records into memory for acquisition
Provide link activity indicators, status, and statistics including ECC error, CRC
error, and HS burst error events.
The DPhy Decoder is controlled from a Windows application called DPhyDecoderHSCtl,
which communicates with the Decoder via a USB connection. Using this application, the
user can monitor DPhy bus activity, select modes of operation, configure the triggering
and functions of the instrument, and initiate the acquisition and capture of DPhy traffic.
In addition, DPhyDecoderHSCtl provides post-processing and protocol disassembly of
acquired data. For those familiar with Tektronix bus support packages that run on the
instrument, the disassembly window of DPhyDecoderHSCtl has a similar look-and-feel.
However, extensive improvements have been made to the basic listing functionality,
providing sophisticated functions for displaying, filtering, and searching captured data.
This includes a packet type summary listing of all packet types in the acquired trace. It
also includes a video frame summary listing that provides statistics, navigation, viewing,
and saving of video frames to files.
The DPhy Decoder HS is a successor instrument to the DPhy Decoder and has several
improvements over its predecessor:
DPhy Decoder HS
Supports up to four lanes @ 2.5 Gbps
Supports DPhy, DSI, CSI-2 version 1.2
Intended to be upgradable for DSI 2.0
1 GB acquisition memory
Efficient, lane-independent data storage
(50% effective data packing)
Supports “Monitor Mode” operation using
solder-down probes
Supports new “Receive Mode” operation
DPhy Decoder
Supports up to four lanes @ 1.5 Gbps
Supports DPhy, DSI, CSI-2 version 1.1
Not upgradable
512 MB acquisition memory
Per-lane data storage (33% effective data
packing at 4 lanes with timestamps)
Supports “Monitor Mode” operation using
solder-down probes
No support for “Receive Mode” operation
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