Download IBM PPC403GCX Embedded Controller User`s Manual

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Table 6-7. Register Settings during Data Machine Check (cont.)
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PC
EVPR[0:15] || 0x0200
BEAR
Written with the address that caused the Machine Check.
BESR
Written with type of machine check.
6.5
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WE, PR, CE, EE, ME, DE, PE ← 0
PX ← unchanged
DR, IR ← 0
ILE ← unchanged
LE ← ILE
MSR
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Data Storage Exception
The Data Storage exception is generated when the desired access to the effective address
is not permitted for any of the following reasons:
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In Problem State with data translation enabled
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•
•
Data store or dcbz to an effective address with the WR bit clear and
(ZPR field) ≠ 11. (The privileged instructions dcbi and dccci are treated as
“stores”, but will cause privileged Program exceptions, rather than Data Storage exceptions.)
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8
9
10
In Supervisor State with data translation enabled
•
•
A zone fault, which is any user-mode storage access (data load, store, icbi,
dcbz, dcbst, or dcbf) with an effective address with (ZPR field) = 00. (dcbt
and dcbtst will no-op in this situation, rather than cause an exception. The
instructions dcbi, dccci, icbt, and iccci, being privileged, cannot cause zone
fault Data Storage exceptions.)
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Data store, dcbi, dcbz, or dccci to an effective address with the WR bit clear
and (ZPR field) other than 11 or 10.
11
In either Problem or Supervisor State with data translation disabled and
MSR[PE] = 1, a Protection Bounds error is detected.
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A Protection Bounds error occurs when a “store” access is attempted to an address
in a protected region. These include data cache operations dcbz and dcbi, but not
dccci. Protected regions are defined by the two pairs of Protection Bound Upper
and Lower registers and the Protection Exclusive Mode bit MSR[PX]. Protection is
enabled by the MSR[PE] bit. A Protection Bounds error can only occur when data
translation is disabled (MSR[DR]=0). If data translation is enabled, then the
Protection Bounds mechanism is disabled, regardless of the state of MSR[PE].
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See Section 9.4.2 (Real-mode Access Protection) on page 9-18 for a detailed
discussion.
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B
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Ver 0.04, 5/07/97
Preliminary
Interrupts, Exceptions, and Timers
6-23
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