Download IBM PPC403GCX Embedded Controller User`s Manual

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9.4.3
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Access Protection for Cache Instructions
Architecturally the instructions dcbi and dcbz are treated as “stores” since they can
change data (or cause loss of data by invalidating a dirty line). Both instructions can
cause protection bounds Data Storage Exceptions, if data translation is disabled.
If data translation is enabled, both dcbi and dcbz can cause WR = 0 data storage
exceptions. dcbz can cause the (ZPR-field) = 00 data storage exception when executed
in user mode; dcbi cannot, since it is a privileged instruction.
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The dccci instruction may also be considered a “store” since it can change data by
invalidating a dirty line; however, dccci is not address-specific (it affects an entire
congruence class regardless of the operand address of the instruction). Because it is
not address-specific, it will not cause bounds exceptions. To restrict possible damage
from an instruction which can change data and yet avoids the protection mechanism,
the dccci instruction is privileged.
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If data translation is enabled, dccci can cause WR = 0 data storage exceptions (the
operand is treated as if it were address-specific). dccci cannot cause (ZPR-field) = 00
data storage exceptions, since it is a privileged instruction.
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Because dccci can cause data storage and TLB-miss exceptions, it is not
recommended to use dccci when MSR[DR] = 1; if it is used, care should be taken that
the specific operand address will not cause an exception.
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Touch instructions are considered “speculative” loads; therefore, if a (ZPR-field) = 00
data storage exception would otherwise result from the execution of dcbt or dcbtst, the
instruction becomes a no-op and the exception does not occur. Similarly, TLB-miss
exceptions do not occur for these instructions.
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Architecturally dcbf and dcbst are treated as “loads”. Flushing or storing a line from the
cache is not architecturally considered a “store” since the store has already been done
to update the cache and the dcbf or dcbst is only updating the main memory’s copy.
Therefore, neither dcbf nor dcbst can cause protection bounds or WR = 0 Data
Storage Exceptions. Since neither of these instructions is privileged, they can both
cause (ZPR-field) = 00 data storage exceptions, if data translation is enabled.
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dcread is a “load” from a non-specific address, and is privileged. Therefore, it does not
receive bounds protection, and cannot cause (ZPR-field) = 00 or WR = 0 data storage
exceptions.
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icbi and icbt are considered “loads”, and so do not receive bounds protection and
cannot cause WR = 0 data storage exceptions. icbi can cause (ZPR-field) = 00 data
storage exceptions, if data translation is enabled. Since icbt is privileged, it cannot
cause (ZPR-field) = 00 data storage exceptions.
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Architecturally dcbt and dcbtst are treated as “loads” since they do not change data;
therefore there is no bounds protection on these instructions and they cannot cause
WR = 0 data storage exceptions.
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PPC403GCX User’s Manual
Preliminary
Ver 0.04, 5/07/97