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THIS FILE USES DATA I/O'S ABEL DESIGN LANGUAGE
TO GENERATE A JEDEC FILE TO PROGRAM AN ALTERA
EP310 ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD).
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MODULE dtack and bus errorgeneration
TITLE
FLAG '-X0'
'DTACK AND BUS ERROR GENERATION FOR THE MINIMAL SYSTEM'
u64 DEVICE 'E0310';
"Abel V2 must be used for this device.
"DEFINE LABELS ASSOCIATED WITH INPUT AND OUTPUT PINS
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FOR THE EP310
INPUT PINS
berr delay,romdelay,sramdelay,romen,
dtack681,sramen PIN 1,8,9,11,13,16;
-
OUTPUT PINS
dtack,berr PIN 18,19;
"ASSIGNMENT
h
1
x
STATEMENTS
= 1;
"HIGH
= 0;
"LOW
"DONT CARE
= .X.;
"DEFINE EQUATIONS
"
NOTE:
! = INVERSION
it
& = AND
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# = OR
EQUATIONS
dtack=(!dtack681)#(sramen&sram delay)#(!romen&romdelay);
berr = berr delay;
END dtackandbus error generation
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