Download MPC8360 MDS Processor Board

Table 5-19. P8 - JTAG/COP Connector (continued)
Pin No.
Signal Name
Description
14
KEY
No pin in connector. Serves for correct plug insertion. See Figure
5-7 for location.
15
Check Stop Output
Machine Check Stop Output
P8
15
1
16 14
2
Figure 5-7. P8 COP connector front view
5.5.7
P9 - FPGA’s In-System-Programming (ISP)
This is a 16 pin generic 0.100" pitch header connector, providing In System Programming capability for
on board programmable logic devices by Xilinx FPGA (Spartan-2E). The pinout of P9 is shown in
Table 5-20. "P9 - FPGA Programming ISP Connector" below:
Table 5-20. P9 - FPGA Programming ISP Connector
5.5.8
Pin No.
Signal Name
Attr.
Description
1
ISP_TDO
I
Transmit Data Output.
2,10,12,
16
GND
P
Main GND plane.
3
ISP_TDI
O
Transmit Data In.
4,5,8,11,1
3,14,15
N.C.
-
Not Connected.
6
SENSE
P
Connect to 3.3V power supply bus via protection
resistor. Use for programmer powering.
7
ISP_TCK
O
Test port Clock.
9
ISP_TMS
O
Test Mode Select.
P10 - Power Connector
P10 is 2mm Power Jack RAPC722 which provides a connection to an external power supply [email protected].
MPC8360 MDS Processor Board, Rev. A
5-22
Freescale Semiconductor