Download MPC8360 MDS Processor Board

5.8.3
Flash Memory
The Flash memory used (see also Section 7.1 on page 7-1) is the MT28F128J3RG-12 from Micron. The
standard unit has 128Mbit, but can be upgraded to 256Mbit by simply inserting the larger volume device
in the socket. The Flash is connected to the slow bus. The slow bus is organized in such a way that the data
is obtained from the data transceiver, and the address is obtained from the address latch buffer.
The Chip Select signal is connected to the CS0~ line for booting from the Flash. A special buffer for
control signals is used in order to minimize the load on the local bus control signals, which are already
used on the SDRAM. Local bus LOE~ control Flash OE and LBS [0-1] control Flash WE~ signals.
The Local Bus A7 is routed to the flash for optional expansion.
The flash output STS signal indicates that either a programming or erase function is being done - this signal
is connected to MPC836X interrupt line.
In order to boot from FLASH SW9[3] should be set to ‘1’.
5.9
GETH
GETH ports features are as follows:
• Support for GMII, TBI, RGMII and RTBI
— (The GETH ports are compatible with RGMII for 10/100-BaseT or GMII, RGMII, TBI and
RTBI for 1000Base-T)
— Default mode: GMII
• When working in PIB Combined Mode (attached to riser connections on PIB) GMII, TBI, RGMII
and RTBI are supported on both the MPC8360 MDS Processor Board and on the PIB.
• Two IEEE 802.3 compliant GETH ports with T.P. (10/100/1000-Base-TX) I/F
• Two PHYs from Marvel (88E1111), connected to ENET1 & ENET2 Pins.
• The two PHYs are controlled and configured via the Processor Board’s BCSR8[0-5] in all modes
— (It is also possible to configure to other PHY configuration modes via the PHY internal
registers)
Note also the following:
Some of the PHY configuration parameters require a Soft Reset to activate the new configuration value.
See PHY documentation (from Marvel) for a list of such parameters.
The PHY reset input is driven by either an assertion of HRST (Hard Reset), or by writing zero to
BCSR9[2]. The registers BCSR9[0,1] are the enable bits for each of the PHYs. Note that whenever
BCSR9[2] is changed from low to high, the value of BCSR8[0-5] is driven to the PHY to configure the
hardware setting.
The PHYs reset any time an HRST (Hard Reset) sequence is taken. The PHY may execute a Soft Reset by
asserting bit 15 (MSB) of the 88E1111 control register 0 via the MDC & MDIO signals.
When the PIB is used only the reduced modes (RGMII and RTBI) are recommended.
Section 5.9.1 to Section 5.9.6 describe in more detail each PHY mode.
MPC8360 MDS Processor Board, Rev. A
Freescale Semiconductor
5-29