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XC164CM System Units (Vol. 1 of 2) General System Control Functions 6.3.1 Status Indication The system status register SYSSTAT indicates the status of the clock generation unit and the recent reset with a number of flags. SYSSTAT System Status Register 15 14 13 12 mem (F1E4H/--) 11 10 OSC PLL OSC CLK CLK PLL LOC LOC STA HIX LOX EM K K B rh rh rh rh rh rh Reset Value: XXXXH 9 8 7 6 5 4 3 2 1 - - - - - - - HW R - - - - - - - rh 0 SW WDT R R rh rh Field Bits Type Description OSCLOCK 15 rh Oscillator Signal Status Bit 0 The oscillator is unlocked 1 The oscillator is locked (2048 fOSC periods have been counted, so it is assumed as stable) PLLLOCK 14 rh PLL Signal Status Bit 0 PLL unlocked (base frequency or adjusting) 1 The PLL is locked (stable output frequency) CLKHIX 13 rh Input Clock High Limit Exceeded 0 The input clock frequency is below the upper limit of the monitored range 1 The input clock frequency is too high CLKLOX 12 rh Input Clock Low Limit Exceeded 0 The input clock frequency is above the lower limit of the monitored range 1 The input clock frequency is too low OSCSTAB 11 rh Oscillator Stable Flag 0 The oscillator is starting up 1 The oscillator counter has reached its upper threshold (215 fOSC periods). With default gain, this indicates that the oscillator has reached 90% of its maximum amplitude. OSCSTAB is cleared upon a hardware reset or after a wakeup trigger when the oscillator was off. User’s Manual SCU_X41, V2.2 6-33 V1.2, 2006-03
