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Ref.:
SpaceWire CODEC IP
User Manual
6.5.8
UoD-Link-User
2.4
Issue: 27 March 2009
Date: Page: 30 / 69
Transmit bit clock configuration TXCLK_SLOWCLK_DIV
The TXCLK_SLOWCLK_DIV configuration can be used when:
An independent transmit clock is required (asynchronous to SYSCLK)
Internal variable data rate generation is required.
An independent 10/5MHz reference clock is required and available externally.
The variable data rate is implemented using a programmable divider which enables a toggle flip-flop.
When the SpaceWire CODEC is performing link start-up (FSM.SEL_SLOW) the input TXCLK is
selected. When link start-up has been performed and a link connection has been established the input
TXRATE determines the data rate. When TXRATE is equal to zero (maximum rate) then XIMAX is
asserted and TXCLK is selected by the glitch free clock multiplexer. When TXRATE is not equal to
zero the clock generator output XI_CLK_DIV is selected by the multiplexer.
XIMAX
=0
FSM.SEL_SLOW
TXRATE
Prog
Divider
XI_DIV_CLK
0
DOUT
XCLK_DIV
TXCLK
DOUT_F
0
TXBITCLK
1
Tx
Encode
SOUT
(Glitch Free Clock Multiplexer)
SLOWCLK
SOUT_F
1
(Glitch Free Clock Multiplexer)
XENR
XENF
Figure 6-8 TX_SLOWCLK_DIV transmit clock configuration
Page 30 of 69