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Download MCF5485 Reference Manual - Freescale Semiconductor
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Virtual Memory Management Architecture Instruction Fetch Pipeline J IAG Branch Cache KC1 IC1 KC2 IC2 Branch Accel. Instruction Memory Physical KC1 IED IB Memory Management Unit (MMU) Operand Execution Pipeline DS Physical KC1 DS J OAG Data Memory KC1 OC1 KC2 OC2 EX M Bus K2M EMAC Misalignment Module FPU DA BDM DSCLK DSI DSDO DDATA PSTDDATA PSTCLK Figure 5-1. CF4e Processor Core Block with MMU 5.2.3 MMU Architecture Implementation This section describes ColdFire design additions and changes for the MMU architecture. It includes precise faults, MMU access, virtual mode, virtual memory references, instruction and data cache addresses, supervisor/user stack pointers, access error stack frame additions, expanded control register space, ACR address improvements, supervisor protection, and debugging in a virtual environment. MCF548x Reference Manual, Rev. 5 Freescale Semiconductor 5-3
