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Download MCF5485 Reference Manual - Freescale Semiconductor
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Table 19-47. PCI Bus Commands (Continued) PCICXBE[3:0] PCI Bus Command MCF548x Supports as Initiator MCF548x Supports as Target Definition 1001 Reserved No No — 1010 Configuration read Yes Yes The configuration read command accesses the 256 byte configuration space of a PCI agent. 1011 Configuration write Yes Yes The configuration read command accesses the 256 byte configuration space of a PCI agent. 1100 Memory read multiple Yes Yes For MCF548, as master the memory read multiple command functions the same as the memory read command. . Cache line wrap is implemented if XL bus is the transaction initiator and also wraps. 1101 Dual address cycle No No The dual address cycle command is used to transfer a 64-bit address (in two 32-bit address cycles) to 64-bit addressable devices. MCF548 device does not respond to this command. 1110 Memory read line Yes Yes The memory read line command indicates that an initiator is requesting the transfer of an entire cache line. For MCF548, the memory read line functions the same as the memory read command. Cache line wrap is not implemented. 1111 Memory write and invalidate Yes (DMA access only) Yes The memory write and invalidate command indicates that an initiator is transferring an entire cache line, and, if this data is in any cacheable memory, that cache line needs to be invalidated. The memory write and invalidate functions the same as the memory write command. Cache line wrap is not implemented. Though MCF548x supports many PCI commands as an initiator, the communication subsystem initiator interface is intended to use PCI memory read and memory write commands. 19.4.1.5 Addressing PCI defines three physical address spaces: PCI memory space, PCI I/O space, and PCI configuration space. Address decoding on the PCI bus is performed by every device for every PCI transaction. Each agent is responsible for decoding its own address. The PCI specification supports two types of address decoding: positive decoding and subtractive decoding (refer to Section 19.4.1.5.4, “Address Decoding). The address space that is accessed depends primarily on the type of PCI command that is used. 19.4.1.5.1 Memory Space Addressing For memory accesses, PCI defines two types of burst ordering controlled by the two low-order bits of the address: linear incrementing(AD[1:0] = 0b00) and cache wrap mode (AD[1:0] = 0b10). The other two AD[1:0] encodings (0b01 and 0b11) are reserved. For linear incrementing mode, the memory address is encoded/decoded using PCIAD[31:2]. Thereafter, the address is incremented by 4 bytes after each data phase completes until the transaction is terminated or completed (a 4 byte data width per data phase is implied). Note, the two low-order bits of the address are still included in all the parity calculations. MCF548x Reference Manual, Rev. 5 19-52 Freescale Semiconductor
