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D
D
D
D
D
R
R
R
R
R
A
A
A
A
A
D
R
R
D
R
D
F
FT
A
A
R
R
D
FT
FT
A
A
R
R
D
D
D
R
A
FT
D
Transmit FIFO not empty
D
Transmit FIFO empty
0
FT
1*
A
Transmit FIFO empty bit
R
R
D
TX_FIFO_EMPTY
FT
FT
FT
0
A
A
A
Description
R
R
R
Access Value
D
D
D
Symbol
FT
FT
FT
FT
Bit
A
A
A
A
R
R
D
D
D
LPC2917/19 - ARM9 microcontroller with CAN and LIN
Table 105. SPI status-register bit description …continued
* = reset value
FT
FT
FT
FT
FT
Preliminary UM
NXP Semiconductors
R
A
3.7.10 SPI slave-settings 1 register
The 1st slave-settings register configures the serial clock rate, the number of words and
the inter-frame delay for each slave of the SPI module.
Table 106. SLVn_SETTINGS1 register bit description
* = reset value
Bit
Symbol
Access Value Description
31 to 24 INTER_TRANSFER_DLY
R/W
The delay between transfers to this
slave, measured in serial clock cycles.
This delay is a minimum of 0 serial clock
cycles[1]
00h*
23 to 16 NUMBER_WORDS
R/W
Number of words to send in sequentialslave mode.
After this number of words has been
transmitted to the slave the master will
start transmitting to the next slave. If
sequential-slave mode is disabled this
field is not used (minus 1 encoded)[1].
00h*
15 to 8
CLK_DIVISOR2
Serial clock-rate divisor 2[2]:
R/W
A value from 2 to 254 (lsb bit is
hard-coded 0)
02h*
7 to 0
CLK_DIVISOR1
Serial clock-rate divisor 1[2]:
R/W
A value from 0 to 255
00h*
[1]
This register is only relevant in master mode, and each individual slave has its own parameters.
[2]
The serial-clock frequency is derived from CLK_SPIx using the values programmed in the CLK_DIVISOR1
and CLK_DIVISOR2 fields:
f ( CLK_SPI )
fserialclk = -------------------------------------------------------------------------------clkdivisor2 × ( 1 + clkdivisor1 )
3.7.11 SPI slave-settings 2 register
The SPI second slave-settings register configures several other parameters for each
slave of the SPI module.
Remark: Some bits in this register are only relevant in master mode, and each individual
slave has its own register with parameters.
UMxxxxx
User manual
© NXP B.V. 2007. All rights reserved.
Rev. 01.02. — 8 November 2007
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