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EDP-AM-DIO54 Digital IO Module User
Manual
This document contains information on the DIO54 digital IO module for the
RS EDP system.
Version v5.0, 10/06/2010
EDP-AM-DIO54 Manual
Contents 1. 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.6 1.7 Digital IO Module
3 Digital Outputs ................................................................................. 3 Using Multiple Digital IO Modules ................................................... 3 Software Drivers For Digital Module ............................................... 3 Digital IO Module Connectors ......................................................... 4 500mA Outputs ............................................................................... 4 I2C GPIO Outputs (25mA) .............................................................. 4 I2C GPIO Inputs (unprotected) ....................................................... 5 Protected Digital Inputs ................................................................... 5 Location Of Module Jumpers And Connectors ............................... 6 Detailed Notes On Configuring The DIO54 Module For Use .......... 7 DIO54 Compatibility ........................................................................ 7 Controlling The DIO54 Digital I/O Module....................................... 7 Digital Outputs ................................................................................. 7 Digital Inputs ................................................................................... 7 Mapping Of CPU Peripheral Pins To The Digital Module ............... 8 Setting The Jumpers And Solder Bridges ....................................... 9 Digital IO Module Jumper Settings ............................................... 11 © Electrocomponents plc
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EDP-AM-DIO54 Manual
1. Digital IO Module
The digital module provides a means to apply digital signals to the CM and drive world devices from it.
There are 12 input channels with overvoltage protection and optional pull-ups, plus another 16 TTL
inputs accessible only via I2C. 16 outputs are present each with a current drive capability of 500mA,
plus another 16, 25mA logic outputs.
The first 12 inputs and 16 outputs are derived from the CM (where possible), although the protected
input stages and high-current output stages can be connected to the I2C IO expander also.
The input I2C ports can generate an interrupt request. This is disabled by default as it could result in a
high CPU interrupt loading.
An RGB colour LED may be fitted for experimental purposes
1.1 Digital Outputs
The 500mA outputs are simple low-side drives and are in the OFF state at power-up. They are
designed to drive relays and solenoids and in fact can sink up to 1A but the user may need to attach a
mini-heatsink to the driver IC if high duty ratios are expected.
It is up to the user to program the digital output pins of the CPU to a logic ‘1’ to turn the outputs on.
There is a net inversion through the drivers so that a logic ‘1’ at the CPU output pin will result in a low
(i.e. current sink enabled) at the output connector.
The user is provided with a software suite of drivers to allow the pins of the IO module to be controlled
both by I2C and also via direct port manipulation of the MCU’s IO pins. All of the CMs provided by
Hitex provide software support for the Digital IO Module
Depending on the CPU module being used, not all of the 12 inputs and 16 outputs can be controlled
independently. This is due to a potential shortage of IO pins on the CPU itself. In such cases, the
duplicated or unavailable channels should be routed to one of the two I2C GPIO devices to make up
the shortfall.
1.2 Using Multiple Digital IO Modules
Up to 3 Digital IO Modules may be fitted to a single baseboard (4 if no CPU is fitted). Typically, the
first module would make use of the CPU module’s own port pins. Other modules would rely on the
I2C GPIO devices for their connection to the CPU. The full 8 I2C slave address variations is available
to all these devices (via solder links on the AM). The user must make sure that there are no conflicts
on IO pins on the backplane when more than one module is fitted. Alternatively, all digital IO modules
could use I2C, freeing up CPU pins for other purposes.
Where a second EDP baseboard is available, the I2C_GEN_0 I2C bus can be used to connect further
digital IO modules.
1.3 Software Drivers For Digital Module
The module has two I2C GPIO devices, both of which require special software drivers to access.
These are provided for each of the CPU Modules. The software allows for control from both I2C bus
commands and also via direct port control from the CPU.
© Electrocomponents plc
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EDP-AM-DIO54 Manual
1.4 Digital IO Module Connectors
1.4.1
500mA Outputs
X202
Description
X202
Description
1
DO0 1A output
2
DO8 1A output
3
DO1 1A output
4
DO9 1A output
5
DO2 1A output
6
DO10 1A output
7
DO3 1A output
8
DO11 1A output
9
DO4 1A output
10
DO12 500mA output
11
13
15
DO5 1A output
DO6 1A output
DO7 1A output
12
14
16
DO13 500mA output
DO14 500mA output
DO15 500mA output
17
DO16_L logic output
18
DO17_L logic output
19
DO18_L logic output
20
DO15 500mA output
21
CPU Vcc
22
12V GND
23
CPU Vcc
24
+12V
Note: Although the outputs DO0 – DO11 are rated at 1 Amp you should take care that the maximum
total ULN2003 power dissipation is not exceeded.
1.4.2
I2C GPIO Outputs (25mA)
X203
Description
X203
Description
1
GPIO OUT_P00
2
GPIO OUT_P10
3
GPIO OUT_P01
4
GPIO OUT_P11
5
GPIO OUT_P02
6
GPIO OUT_P12
7
GPIO OUT_P03
8
GPIO OUT_P13
9
GPIO OUT_P04
10
GPIO OUT_P14
11
GPIO OUT_P05
12
GPIO OUT_P15
13
GPIO OUT_P06
14
GPIO OUT_P16
15
GPIO OUT_P07
16
GPIO OUT_17
17
CPU Vcc
18
+3V3
19
+5V
20
SGND
© Electrocomponents plc
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EDP-AM-DIO54 Manual
1.4.3
I2C GPIO Inputs (unprotected)
X204
Description
X204
Description
1
GPIO IN_P00
2
GPIO IN_P10
3
GPIO IN_P01
4
GPIO IN_P11
5
GPIO IN_P02
6
GPIO IN_P12
7
GPIO IN_P03
8
GPIO IN_P13
9
GPIO IN_P04
10
GPIO IN_P14
11
GPIO IN_P05
12
GPIO IN_P15
13
GPIO IN_P06
14
GPIO IN_P16
15
GPIO IN_P07
16
GPIO IN_P17
17
CPU Vcc
18
+3V3
19
+5V
20
SGND
1.4.4
Protected Digital Inputs
X205
Description
X205
Description
1
DI0 input
2
DI8 input
3
DI1 input
4
DI9 input
5
DI2 input
6
DI10 input
7
DI3 input
8
DI11 input
9
DI4 input
10
DI12 input
11
DI5 input
12
DI13 input
13
DI6 input
14
DI14 input
15
DI7 input
16
DI15 input
17
CPU Vcc
18
+3V3
19
+5V
20
SGND
© Electrocomponents plc
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EDP-AM-DIO54 Manual
1.4.5
Location Of Module Jumpers And Connectors
Top View
© Electrocomponents plc
Bottom View
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EDP-AM-DIO54 Manual
1.5 Detailed Notes On Configuring The DIO54 Module For Use
1.5.1
DIO54 Compatibility
The DIO54 module has been designed as a universal module which can accept any processor
modules designed for the EDP system. As such it is important to note that there are a few limitations
which the user needs to be aware of. You must check that the DIO54 is correctly configured for your
CPU before fitting it to the EDP baseboard!
1.5.2
Controlling The DIO54 Digital I/O Module
This module can be controlled by the CPU in several ways. On board the module are two independent
serial I/O latch devices. Each of these devices has an input mode and an output mode function. The
PCB has been designed such that one device is dedicated to output mode and the other device is
dedicated for input mode. The chip used is the NXP PCA9555 device.
The PCA9555 device can be controlled via the I2C0 channel on the CPU via the back plane. This
I2C0 channel is referred to as the CNTRL I2C channel on the Baseboard. Each of the two PCA9555
devices has its own unique I2C address to communicate on.
1.5.3
Digital Outputs
The PCA9555A device can be used to output data, the raw logic level output signals for this are
referred to as OUT_P0(x) and OUT_P1(x) where x = 0 to7. These signals are available to probe on
connector X203, and there are 16 logic level outputs in total. These raw logic level outputs can be fed
into a high current Darlington driver of the type ULN2003. This however is a board option and the user
has to configure the board to do this via a series of solder bridges. These bridges are B501-B508 and
B602-B609. Check the board to ensure they are configured how you want them.
The Darlington drive output from the ULN2003 appears on another connector X202, as signal DO(y)
where y = 0 to 15. Note the output drive of DO(0)-DO(11) is double that of DO(12)-DO(15), due to the
way the hardware has been implemented.
The CPU also has some direct I/O capability and this feature is bought out onto the Baseboard. The
Digital I/O Module has access to these signals and the user can use these rather than the signals
produced by the I2C PCA9555 digital latches. On the Digital I/O Module these signals are referred to
as EDP_DO(y) where y = 0 to 15.
The mapping between the CPU’s port pins and the Output on the D0(y) pins is given later.
1.5.4
Digital Inputs
The Digital I/O Module can also read in external input signals via an input buffer. The real world
signals are referred to as DI(y) where y = 0 to 15. Signals DI(0) to DI(11) have an input protection
stage and hex Schmitt trigger inverting buffer input whilst signals DI(12) to DI(15) have a different
input protection arrangement. There are no buffers or inversion of these signals.
The input signals after the protection stage can be routed via jumper links to either the serial input
latches or to the STR9 MCU I/O pins. Jumpers J400 and J401 provide routing for 12 inputs DI(0) to
DI(11) whilst input DI(12) to DI(15) have no routing capability and are fed directly into one of the
PCA9555 serial latch device. The signals which are passed into the latches are referred to as
IN_P0(x) and IN_P1(x) where x = 0 to 7, whilst the signals which pass directly into the MCU pins are
referred to as EDP_DI(z) where z=0 to 11.
© Electrocomponents plc
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EDP-AM-DIO54 Manual
There is no problems at all when the devices are configured as serial latch input device, although it’s
worth noting that the same logic level when presented to DI(0) to DI(11) will read differently when
presented to DI(12) to DI(15). This is because the DI(0) to DI(11) inputs have the Schmitt inverter in
series with them.
When the link options are organised for direct input digital reading it’s worth noting that there may be a
share conflict with other modules that may require these I/O pins as output pins.
1.5.5
Mapping Of CPU Peripheral Pins To The Digital Module
The mapping of the various CPU modules to the backplane is different for each CPU Module. This
means the digital IO Module appears slightly differently for each CM that is fitted. An example of the
mapping is shown below for two CPU modules. The provided software allows for easy reading and
writing of values to the Digital IO Module. The software is different for each Command Module.
XC167 Pin Allocation Vcc to BB STR9 Pin Allocation Vcc 3V3 or 5V, supplied by CM EDP‐AM‐DIO54 Allocation Vcc 3V3 or 5V, supplied by CM P3.5 P3.2 9 P6.2/CC2IO 8 P6.1/CC1IO 56 P2.15/CC15IO 55 P2.14/CC14IO 54 P2.13/CC13IO 53 P2.12/CC12IO 52 P2.11/CC11IO 51 P2.10/CC10IO 13 P6.6/CC6IO 12 P6.5/CC5IO 11 P6.3/CC4IO 10 P6.3/CC3IO 50 P2.9/CC9IO 49 P2.8/CC8IO P3.7 Digital GND Vcc 5V from reg P5.7 P5.6 P6.0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.0 P6.4 P6.3 P6.2 P6.1 P4.1 P4.0 P7.4 Digital GND 5V from baseboard regulator 3V3 from baseboard regulator 12V Power GND 12V Power GND +12V 2A +12V 2A IRQ_GPIO18_I2C GEN0 INT IRQ_GPIO16_CNTRL I2C INT EDP_DO9 EDP_DO8 EDP_DO7 EDP_DO6 EDP_DO5 EDP_DO4 EDP_DO3 EDP_DO2 EDP_DO13 EDP_DO12 EDP_DO11 EDP_DO10 EDP_DO1 EDP_DO0 EDP_DI11 Digital GND 5V from baseboard regulator Vcc 3V3 from reg 12V Power GND 12V Power GND +12V 2A +12V 2A © Electrocomponents plc
3V3 from baseboard regulator 12V Power GND 12V Power GND +12V 2A +12V 2A Page 8
EDP-AM-DIO54 Manual
XC167 Pin Allocation Vcc to BB STR9 Pin Allocation Vcc 3V3 or 5V, supplied by CM EDP‐AM‐DIO54 Allocation Vcc 3V3 or 5V, supplied by CM 24 P9.3/CC19IO 55 P2.14/CC14IO 56 P2.15/CC15IO 21 P9.0/CC16IO 22 P9.1/CC17IO 23 P9./2CC18IO 131 P1H.4/CC24IO 132 P1H.5/CC25IO 133 P1H.6/CC26IO 134 P1H.7/CC27IO 15 P7.4/CC28IO 16 P7.5/CC29IO 17 P7.6/CC30IO P7.7/CC31IO (CS8900A INT) 124 P1L.7/CC22IO 124 P1L.7/CC22IO 127 P1H.0/CC23IO Digital GND Vcc 5V from reg P4.0 P0.1 P6.5 P4.6 P4.4 P4.2 P6.7 P6.6 P7.7 P7.6 P7.3 P7.2 P7.1 (PHY disabled) NC EDP_DO18 EDP_DO17 EDP_DO16 EDP_DO15 EDP_DO14 EDP_DI9 EDP_DI8 EDP_DI7 EDP_DI6 EDP_DI5 EDP_DI4 EDP_DI3 P7.0 P0.6 (PHY disabled) P0.5 (PHY disabled) P0.4 (PHY disabled) Digital GND 5V from baseboard regulator 3V3 from baseboard regulator 12V Power GND 12V Power GND +12V 2A +12V 2A EDP_DI2 EDP_DI10 EDP_DI1 EDP_DI0 Digital GND 5V from baseboard regulator Vcc 3V3 from reg 12V Power GND 12V Power GND +12V 2A +12V 2A 3V3 from baseboard regulator 12V Power GND 12V Power GND +12V 2A +12V 2A XC167 Pin Allocation Vcc 5V from reg Vcc 3V3 or 5V, supplied by CPU Vcc 3V3 from reg STR9 Pin Allocation Vcc 5V from reg Vcc 3V3 or 5V, supplied by CPU Vcc 3V3 from reg EDP‐AM‐DIO54 Allocation Vcc 5V from reg Vcc 3V3 or 5V, supplied by CPU Vcc 3V3 from reg 26 SCL2 P2.0 EDPCON2.79 25 SDA2 24 SCL1 23 SDA1 Digital GND P2.1 P2.2 P2.3 Digital GND EDPCON2.77 EDPCON2.7 EDPCON2.5 Digital GND Note: The shaded signals are not available with certain CPU modules. These inputs and outputs are
recommended to be connected to the appropriate I2C GPIO device rather than relying on the CPU’s
own port pins.
1.6 Setting The Jumpers And Solder Bridges
To make the Digital I/O Module compatible with direct MCU drive from the I/O pins the solder jumpers
mentioned above, B501-B508 and B602-B609 need to be set accordingly. This means the user has
the option to drive the output directly from the MCU’s or via the PCA9555 serial latch depending on
the jumper options.
In terms of compatibility with other modules it is worth noting that the STR9 has on board ADC. These
ADC channels are on Port4, so there is a potentially conflicting situation when used with the Analogue
Module. I.e. The analogue module will present analogue values to Port4 whilst Port4 is trying to drive
© Electrocomponents plc
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EDP-AM-DIO54 Manual
the Digital Module outputs. It is therefore prudent to reserve the Port4 pins for analogue input whilst
using the Port6 pins for digital output. This means having some idea of what MCU system resources
you will require in your design and modifying both the source code and the hardware to suite.
The low level hardware drivers may therefore need to be modified when mixing modules to avoid this
potential conflict.
The Digital I/O Module can also read in external input signals via an input buffer. The real world
signals are referred to as DI(y) where y = 0 to 15. Signals DI(0) to DI(11) have an input protection
stage and hex Schmitt trigger inverting buffer input whilst signals DI(12) to DI(15) have a different
input protection arrangement. There are no buffers or inversion of these signals.
The input signals after the protection stage can be routed via jumper links to either the serial input
latches or to the STR9 MCU I/O pins. Jumpers J400 and J401 provide routing for 12 inputs DI(0) to
DI(11) whilst input DI(12) to DI(15) have no routing capability and are fed directly into one of the
PCA9555 serial latch device. The signals which are passed into the latches are referred to as
IN_P0(x) and IN_P1(x) where x = 0 to 7, whilst the signals which pass directly into the MCU pins are
referred to as EDP_DI(z) where z=0 to 11.
There is no problems at all when the devices are configured as serial latch input device, although it’s
worth noting that the same logic level when presented to DI(0) to DI(11) will read differently when
presented to DI(12) to DI(15). This is because the DI(0) to DI(11) inputs have the Schmitt inverter in
series with them.
When the link options are organised for direct input digital reading it’s worth noting that there may be a
share conflict with other modules that may require these I/O pins as output pins.
© Electrocomponents plc
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EDP-AM-DIO54 Manual
1.7 Digital IO Module Jumper Settings
Before fitting the DIO54 module to your EDP baseboard, you must configure the jumpers and solder
bridges to suit the CPU module you are intending to use. The possible settings are given in the
following table.
Jumper
Type
Purpose
Default State
B300
Cut & Solder
Set operating voltage of I2C GPIO devices
Use CPU's Vcc
1-2
B301
B302
B303
B304
B305
B306
B307
B308
B309
B310
B311
B312
B313
B314
B400
B401
B402
B403
B404
B405
B406
B407
B408
B409
B410
B411
B412
B413
B414
B415
Cut & Solder
Cut & Solder
Cut & Solder
Cut & Solder
Cut & Solder
Cut & Solder
Cut & Solder
Cut & Solder
Cut & Solder
Solder
Solder
Solder
Solder
Solder
Cut
Cut
Cut
Cut
Cut
Cut
Cut
Cut
Cut
Cut
Cut
Cut
Cut
Cut
Cut
Cut
Select which I2C channel interrupt to use with both I2C GPIO devices
Set address bit A0 for U300 (input) I2C GPIO device
Set address bit A1 for U300 (input) I2C GPIO device
Set address bit A2 for U300 (input) I2C GPIO device
Set address bit A0 for U301 (output) I2C GPIO device
Set address bit A1 for U301 (output) I2C GPIO device
Set address bit A2 for U301 (output) I2C GPIO device
Select I2C_CTRL bus or I2C GEN0 bus
Select I2C_CTRL bus or I2C GEN0 bus
Bypass PCA9306
Bypass PCA9306
Connect blue LED in RGB array to DO0
Connect green LED in RGB array to DO0
Connect red LED in RGB array to DO0
Pull up DI0 digital input to DIO54 module
Pull up DI1 digital input to DIO54 module
Pull up DI2 digital input to DIO54 module
Pull up DI3 digital input to DIO54 module
Pull up DI4 digital input to DIO54 module
Pull up DI5 digital input to DIO54 module
Pull up DI6 digital input to DIO54 module
Pull up DI7 digital input to DIO54 module
Pull up DI8 digital input to DIO54 module
Pull up DI9 digital input to DIO54 module
Pull up DI10 digital input to DIO54 module
Pull up DI11 digital input to DIO54 module
Pull up DI12 digital input to DIO54 module
Pull up DI13 digital input to DIO54 module
Pull up DI14 digital input to DIO54 module
Pull up DI15 digital input to DIO54 module
I2C_CTRL INT
A0=0
A1=1
A2=0
A0=1
A1=1
A2=0
I2C_CTRL
I2C_CTRL
Not Bypassed
Not Bypassed
Not connected
Not connected
Not connected
Pulled-up
Pulled-up
Pulled-up
Pulled-up
Pulled-up
Pulled-up
Pulled-up
Pulled-up
Pulled-up
Pulled-up
Pulled-up
Pulled-up
Pulled-up
Pulled-up
Pulled-up
Pulled-up
1-2
1-2
2-3
1-2
2-3
2-3
1-2
1-2
1-2
Open
Open
Open
Open
Open
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
= CPU output option may not be available with all EDP CPU modules
© Electrocomponents plc
Page 11
Default
EDP-AM-DIO54 Manual
Jumpe
r
B501
Type
Purpose
Default State
J400A
Cut &
Solder
Cut &
Solder
Cut &
Solder
Cut &
Solder
Cut &
Solder
Cut &
Solder
Cut &
Solder
Cut &
Solder
Cut &
Solder
Cut &
Solder
Cut &
Solder
Cut &
Solder
Cut &
Solder
Cut &
Solder
Cut &
Solder
Cut &
Solder
Jumper
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Connect ULN2003 input to either CPU output pin or U301 I2C GPIO
device
Route DI0 input to CPU digital input pin via EDP or to I2C GPIO U300
J400B
Jumper
Route DI0 input to CPU digital input pin via EDP or to I2C GPIO U300
J400C
Jumper
Route DI0 input to CPU digital input pin via EDP or to I2C GPIO U300
J400D
Jumper
Route DI0 input to CPU digital input pin via EDP or to I2C GPIO U300
J400E
Jumper
Route DI0 input to CPU digital input pin via EDP or to I2C GPIO U300
J400F
Jumper
Route DI0 input to CPU digital input pin via EDP or to I2C GPIO U300
J401A
J401B
J401C
J401D
J401E
J401F
Jumper
Jumper
Jumper
Jumper
Jumper
Jumper
Route DI0 input to CPU digital input pin via EDP or to I2C GPIO
Route DI0 input to CPU digital input pin via EDP or to I2C GPIO
Route DI0 input to CPU digital input pin via EDP or to I2C GPIO
Route DI0 input to CPU digital input pin via EDP or to I2C GPIO
Route DI0 input to CPU digital input pin via EDP or to I2C GPIO
Route DI0 input to CPU digital input pin via EDP or to I2C GPIO
B502
B503
B504
B505
B506
B507
B508
B602
B603
B604
B605
B606
B607
B608
B609
U300
U300
U300
U300
U300
U300
= CPU output option may not be available with all EDP CPU modules
© Electrocomponents plc
Page 12
CPU output
Defaul
t
1-2
CPU output
1-2
CPU output
1-2
CPU output
1-2
CPU output
1-2
CPU output
1-2
CPU output
1-2
CPU output
1-2
CPU output
1-2
CPU output
1-2
CPU output
1-2
CPU output
1-2
CPU output
1-2
CPU output
1-2
CPU output
1-2
CPU output
1-2
Use CPU
input
Use CPU
input
Use CPU
input
Use CPU
input
Use CPU
input
Use CPU
input
Not fitted
Not fitted
Not fitted
Not fitted
Not fitted
Not fitted
1-2
1-2
1-2
1-2
1-2
1-2
Open
Open
Open
Open
Open
Open
EDP-AM-DIO54 Manual
DIO54 ‐ Digital I/O Module Inputs to RS‐EDP Backplane
X205 Digital Input Connector
EVM0_GPIO21
J400
1
EVM1_GPIO23
EVM2_GPIO41_CAPADC
EVM3_GPIO43
EVM4_GPIO45
EVM5_GPIO47
EVM6_GPIO49
EVM7_GPIO51
EVM8_GPIO53
EVM9_GPIO55
EVM10_GPIO68_ASCO_CTS
J400
4
IRQ_GPIO22_I2C_INT
1
IRQ_GPIO16_CNTRL_I2C_INT
IRQ_GPIO18_I2C_GEN0_INT
CNTRL I2C
1
3
B308
2
1
I2C GEN0
7
J400
10
J400
13
J400
16
J401
1
J401
4
J401
7
J401
10
J401
13
J401
16
6
9
12
15
18
3
6
2
5
8
11
14
17
2
5
8
9
12
15
18
11
14
17
I2C Data
I2C CLK
DI(0)
DI(1)
DI(2)
DI(3)
DI(4)
DI(5)
DI(6)
DI(7)
DI(8)
DI(9)
DI(10)
DI(11)
DI(12)
DI(13)
DI(14)
DI(15)
B301
2
3
2
3
J400
3
I2C
B309
DI(0) – DI(11) can be read via I2C or via backplane by the MCU
DI(12) – DI(15) can only be read via I2C.
Mapping Aid summary of Digital Input jumpers and IO configuration
You can see from this diagram that inputs DI(0) to DI(15) provide the digital input pins to the system.
The processed inputs are then made available on the backplane via the link options marked above as
a diamond. If the inputs are required to be read via the I2C bus then the link can be set differently.
DI(12) to DI(15) can only be read via the back plane and no I2C read option is available to them.
The I2C interface can be selected as either CNTRL_I2C, which is the main I2C bus within the RS-EDP
system or via the I2C_GEN0 bus which is usually provided as the user own I2C independent I2C bus.
Not all CMs have two I2C channels so the default is usually CNTRL_I2C. Software drivers are
provided for all the CMs to talk to the Digital IO Modules over the I2C protocol.
The I2C device can generate an interrupt if required. The user can select this interrupt source via the
link options shown above.
© Electrocomponents plc
Page 13
EDP-AM-DIO54 Manual
DIO54 ‐ Digital I/O Module Outputs to RS‐EDP Backplane
X202 Digital Output Connector
EVG0_GPIO40
EVG1_GPIO42
EVG2_GPIO44
EVG3_GPIO46
EVG4_GPIO48
EVG5_GPIO50
EVG6_GPIO52
EVG7_GPIO54
EVG8_GPIO56
EVG10_GPIO58
EVG12_GPIO60
EVG14_GPIO62
B501
1
B502
1
B503
1
B504
1
B505
1
B506
1
B507
1
B508
1
B602
1
B603
1
B604
1
B605
1
EVG16_GPIO64
EVG18_GPIO66
EVG11_GPIO59
EVG13_GPIO61
B606
1
B607
1
B608
1
B609
1
EVG15_GPIO63
EVG17_GPIO65
EVG19_GPIO67
CNTRL I2C
1
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
DO(0)
DO(1)
DO(2)
DO(3)
DO(4)
DO(5)
DO(6)
DO(7)
DO(8)
DO(9)
DO(10)
DO(11)
2
2
2
2
2
2
2
2
2
2
2
2
DO(12)
DO(13)
DO(14)
DO(15)
2
2
2
DO(16)
DO(17)
DO(18)
B308
2
1
2
3
I2C GEN0
3
I2C Data
I2C CLK
X500 GND Terminal
I2C
B509
B309
X500
DO(0) – DO(15) are Darlington outputs, controlled by either I2C or direct MCU control
DO(16) – DO(18) are MCU logic level outputs controlled only by direct MCU
12VGND
Mapping Aid summary of Digital Output jumpers and IO configuration
As you can see from the diagram above the Digital IO Module can be fed with output data either
directly from the back plane signals EVG0 to EVG19 or via I2C packets from the I2C buses. The user
can select which of these two he wishes to use via the link options shown in the diamonds above.
The diagram shows the same I2C bus interface which can be selected to be the same as the input
module. i.e. CNTRL_I2C or I2C_GEN0
Note also the large X500 ground terminal which can be used to terminate large high current switching
loads. As the backplane connections are only rated for up to 2A, for higher current loads the user
should connect the high side load to the IO pin and use the X500 ground terminal for the return current
from the load.
Software drivers are provided for each CM to talk directly to the Digital IO Outputs both by I2C and
also by direct MCU port control.
© Electrocomponents plc
Page 14
12
11
10
9
8
7
6
5
4
3
2
1
H
H
EDP Digital I/O Module
G
G
RS-EDP-DIO54-A1
F
[1]
[2]
[3]
[4]
[5]
[6]
E
D
F
Contents
Connectors
I2C to 16bit Bus; LEDs
Input Protection
Output Drivers (Part 1)
Output Drivers (Part 2)
E
D
C
C
B
B
Rev. Date
Name
1
06.03.2008 Ar
Title
hitex
Contents
DEVELOPMENT TOOLS
This document may not be passed
on, duplicated or its contents utilized,
unless expressly permitted. Violating
this stipulation will result in the liability
to pay damages. All rights reserved
in case of a patent registration or
registered design.
A
12
11
10
9
8
7
6
5
4
3
Board
A
RS-EDP-DIO54-A1
Sheet
01
of
06
File modified 02.04.2008 15:40:00
2
1
12
H
11
5G2, 6G2
10
9
8
7
DO[0]
DO[1]
DO[2]
DO[3]
DO[4]
DO[5]
DO[6]
DO[7]
DO16_L
DO18_L
G
6B7
6A7
VCC
VCC
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
DO[8]
DO[9]
DO[10]
DO[11]
DO[12]
DO[13]
DO[14]
DO[15]
DO17_L
DO[15]
6B7
GND
+12V
S2*12/2.54/SMD
OUT_P0
3C5
OUT_P1
3C1
EDPCON1.37
EDPCON1.39
3G6
3G6
X203
E
OUT_P0[0]
OUT_P0[1]
OUT_P0[2]
OUT_P0[3]
OUT_P0[4]
OUT_P0[5]
OUT_P0[6]
OUT_P0[7]
PCF8575_V
3H7
+5V
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
EDP_DI[11]
OUT_P1[0]
OUT_P1[1]
OUT_P1[2]
OUT_P1[3]
OUT_P1[4]
OUT_P1[5]
OUT_P1[6]
OUT_P1[7]
EDP_DO
5G11, 6G11
+3.3V
GND
IN_P0
IN_P1
D
VCC
+5V
C
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
3E3
IN_P1[0]
IN_P1[1]
IN_P1[2]
IN_P1[3]
IN_P1[4]
IN_P1[5]
IN_P1[6]
IN_P1[7]
S2*10/2,54/TSM
4F12, 4C5
X205
DI[0]
DI[1]
DI[2]
DI[3]
DI[4]
DI[5]
DI[6]
DI[7]
B
VCC
+5V
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
+3.3V
GND
DI
n.c.
EDP_DO[0]
EDP_DO[1]
EDP_DO[2]
EDP_DO[3]
EDP_DO[4]
EDP_DO[5]
EDP_DO[6]
EDP_DO[7]
EDP_DO[8]
EDP_DO[9]
EDP_DO[10]
EDP_DO[11]
EDP_DO[12]
EDP_DO[13]
X204
IN_P0[0]
IN_P0[1]
IN_P0[2]
IN_P0[3]
IN_P0[4]
IN_P0[5]
IN_P0[6]
IN_P0[7]
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
EDP_DI
4H5
S2*10/2,54/TSM
3E7
5
4
DI[8]
DI[9]
DI[10]
DI[11]
DI[12]
DI[13]
DI[14]
DI[15]
(Vcc supplied by CM)
(3.3V from baseboard regulator)
(5V from baseboard regulator)
(Digital GND)
(+12V 2A)
(+12V 2A)
5B5
5B5
+3.3V
GND
S2*10/2,54/TSM
A
VCC
+3.3V
+5V
GND
+12V
+12V
EDP12VGND
EDP12VGND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
2
1
H
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
EDP_DI[0]
EDP_DI[1]
11
10
9
8
7
G
X201
EDP_DI
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
EDP_DI[2]
EDP_DI[3]
EDP_DI[4]
EDP_DI[5]
EDP_DI[6]
EDP_DI[7]
EDP_DI[8]
EDP_DI[9]
n.c.
4H5
EDP_DO
EDP_DO[14]
EDP_DO[15]
EDP_DO[16]
EDP_DO[17]
EDP_DO[18]
EDP_DI[10]
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
1
n.c.
3
n.c.
EDPCON2.5
5
3D12
EDPCON2.7
7
3D12
9
(Digital GND) GND
11
n.c.
13
n.c.
15
n.c.
17
n.c.
19
n.c.
21
n.c.
23
n.c.
25
n.c.
27
n.c.
29
n.c.
31
n.c.
33
n.c.
35
n.c.
37
n.c.
39
n.c.
41
n.c.
43
n.c.
45
n.c.
47
n.c.
49
n.c.
n.c. 51
53
n.c.
6G11, 6A12
55
n.c.
57
n.c.
59
n.c.
61
n.c.
63
n.c.
65
n.c.
67
n.c.
69
n.c.
71
n.c.
73
n.c.
75
n.c.
EDPCON2.77
77
3D12
EDPCON2.79
79
3D12
n.c. 81
n.c. 83
85
n.c.
87
n.c.
n.c. 89
n.c. 91
93
(Vcc supplied by CM) VCC
95
(3.3V from baseboard regulator) +3.3V
97
(5V from baseboard regulator) +5V
99
(Digital GND) GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
n.c.
n.c.
n.c.
n.c.
GND
(Digital GND)
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
F
E
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
D
C
n.c.
n.c.
n.c.
n.c.
VCC
+3.3V
+5V
GND
(Vcc supplied by CM)
(3.3V from baseboard regulator)
(5V from baseboard regulator)
(Digital GND)
B
S2*50/S/AMP
VCC
+3.3V
+5V
GND
+12V
+12V
EDP12VGND
EDP12VGND
(Vcc supplied by CM)
(3.3V from baseboard regulator)
(5V from baseboard regulator)
(Digital GND)
(+12V 2A)
(+12V 2A)
5B5
5B5
Rev. Date
Name
1
06.03.2008 Ar
6
5
Title
hitex
Connectors
DEVELOPMENT TOOLS
This document may not be passed
on, duplicated or its contents utilized,
unless expressly permitted. Violating
this stipulation will result in the liability
to pay damages. All rights reserved
in case of a patent registration or
registered design.
S2*70/S/AMP
12
3
X200
DO
X202
F
6
4
3
Board
A
RS-EDP-DIO54-A1
Sheet
02
of
06
File modified 02.04.2008 15:40:00
2
1
12
11
10
9
8
H
7
VCC
6
5
4
3
2
1
H
+5V
B300
1 2
3
PCF8575_V
2E12
VCC
PCF8575_V
2D12, 4G5
12
23
SDA
22
SCL
4*100R
RA300
1
8
2
7
3
6
4
5
1
8
2
7
3
6
4
5
IN_P0
4
5
6
7
8
9
10
11
4*100R
RA301
INT_N
P00
P01
P02
P03
P04
P05
P06
P07
A0
A1
A2
P10
P11
P12
P13
P14
P15
P16
P17
EDPCON2.79
B304
3 2
13
14
15
16
17
18
19
20
1
GND
IN_P1[0]
IN_P1[1]
IN_P1[2]
IN_P1[3]
IN_P1[4]
IN_P1[5]
IN_P1[6]
IN_P1[7]
F
4*100R
RA303
PCF8575TS
IN_P1
GND
EN
4
SDA1
3
SCL1
7
4K7
4K7
R335
U301
C301
220K
VREF2
R333
VREF1
PCF8575_V
VSS
12
PCF8575_V
GND
1
PCA9306DP1
4*100R
RA304
1
8
2
7
3
6
4
5
5
4
6
3
7
2
8
1
OUT_P0[0]
OUT_P0[1]
OUT_P0[2]
OUT_P0[3]
OUT_P0[4]
OUT_P0[5]
OUT_P0[6]
OUT_P0[7]
B310
2
B311
1
VDD
GND
8
5
SDA2
6
SCL2
1
24
100n
3
B309
EDPCON2.7
GND
1 2
2G4
3
2C4
EDPCON2.5
1 2
D
1
B308
2C4
1
E
U302
2G4
3 2
4*100R
RA302
1
8
2
7
3
6
4
5
8
1
7
2
6
3
5
4
GND
2
EDPCON2.77
3 2
2D9, 4A5, 4D1
R334
+3.3V
B302
1
B303
21
2
3
100n
E
PCF8575_V
GND
1
3
PCF8575_V
C302
G
VSS
100n
IN_P0[0]
IN_P0[1]
IN_P0[2]
IN_P0[3]
IN_P0[4]
IN_P0[5]
IN_P0[6]
IN_P0[7]
F
VDD
1 2
B301
EDPCON1.39
2F8
24
GND
EDPCON1.37
2F8
C300
10K
N.M.
R300
U300
G
2
4
5
6
7
8
9
10
11
4*100R
RA305
C
OUT_P0
INT_N
23
SDA
22
SCL
P00
P01
P02
P03
P04
P05
P06
P07
A0
A1
A2
P10
P11
P12
P13
P14
P15
P16
P17
PCF8575TS
21
2
3
13
14
15
16
17
18
19
20
B305
1
B306
3 2
3 2
1
B307
3 2
1
4*100R
RA307
1
8
2
7
3
6
4
5
8
1
7
2
6
3
5
4
D
GND
OUT_P1[0]
OUT_P1[1]
OUT_P1[2]
OUT_P1[3]
OUT_P1[4]
OUT_P1[5]
OUT_P1[6]
OUT_P1[7]
OUT_P1
4*100R
RA306
2F9, 6G8
C
2F12, 5G8
+5V
DO[0]
DO[1]
B
DO[2]
B312
1
2
B313
1
2
B314
1
2
D300
1
6
R336
68R
R337
47R
R338
120R
PB
2
5
B
VG
3
4
SURK
5G2
LED_RGB_3216
DO
Rev. Date
Name
1
06.03.2008 Ar
Title
hitex
DEVELOPMENT TOOLS
This document may not be passed
on, duplicated or its contents utilized,
unless expressly permitted. Violating
this stipulation will result in the liability
to pay damages. All rights reserved
in case of a patent registration or
registered design.
A
12
11
10
9
8
7
6
5
4
3
I2C to 16bit Bus;
LEDs
Board
A
RS-EDP-DIO54-A1
Sheet
03
of
06
File modified 02.04.2008 15:40:00
2
1
12
11
10
9
8
7
6
5
4
3
2
1
VCC
1N4148
EDP_DI[1]
EDP_DI[2]
EDP_DI[3]
EDP_DI[4]
EDP_DI[5]
VCC
IN_P0[1]
IN_P0[2]
F
IN_P0[3]
IN_P0[4]
IN_P0[5]
V411
E
4*4K7
2
B415 1
4RA4045
3
6
2
7
1
8
V410
V409
V408
V407
4*4K7
IN_P1
3E3
4RA4055
3
6
2
7
1
8
R432
R433
R434
R435
V429
V430
V431
BZM55B6V2
BZM55B6V2
2
2
2
2
B408 1
B409 1
B410 1
B411 1
EDP_DI[6]
C401
4*10K
RA403
1
8
2
7
3
6
4
5
10K
R416
10K
R417
100n
GND
14
1
3
5
9
11
13
U401
VCC GND
7
2 GND
1A
1Y
4
2A
2Y
6
3A
3Y
8
4A
4Y
10
5A
5Y
12
6A
6Y
74HC14PW
EDP_DI[7]
EDP_DI[8]
EDP_DI[9]
EDP_DI[10]
EDP_DI[11]
1
2
4
7
8
10
13
14
16
IN_P0[6]
3
5
6
9
11
12
15
17
18
IN_P0[7]
IN_P1[0]
DI
2C9
1n
1n
1n
1n
2
D
C402
C403
C404
C405
V428
BZM55B6V2
2
B407 1
DI[6]
DI[7]
DI[8]
DI[9]
DI[10]
DI[11]
B406 1
J401
C
IN_P1[4]
IN_P1[5]
IN_P1[6]
IN_P1[7]
180R
180R
180R
180R
4*10K
VCC
BZM55B6V2
R423
4K7
4RA4025
3
6
2
7
1
8
R422
4K7
2
1N4148
V417
DI[12]
DI[13]
DI[14]
DI[15]
GND
D
B414 1
1N4148
V416
BZM55B6V2
1N4148
V415
BZM55B6V2
1N4148
V414
BZM55B6V2
1N4148
V413
BZM55B6V2
1N4148
V412
BZM55B6V2
VCC
E
BZM55B6V2
V406
S3*6/2,54/TSM
1N4148
7
2 GND
1A
1Y
4
2A
2Y
6
3A
3Y
8
4A
4Y
10
5A
5Y
12
6A
6Y
74HC14PW
1N4148
U400
VCC GND
V427
1
3
5
9
11
13
1N4148
14
100n
V426
C400
3E7
1N4148
2
B405 1
GND
3
5
6
9
11
12
15
17
18
V425
2
B404 1
4*10K
RA401
1
8
2
7
3
6
4
5
10K
R404
10K
R405
1
2
4
7
8
10
13
14
16
IN_P0[0]
2
2
B403 1
IN_P0
J400
EDP_DI[0]
2
2
B402 1
EDP_DI
B413 1
F
2
DI[0]
DI[1]
DI[2]
DI[3]
DI[4]
DI[5]
2
DI
B401 1
2C9
B400 1
2F5, 2F8
V424
VCC
B412 1
1N4148
V405
R411
G
4K7
1N4148
V404
1N4148
V403
1N4148
V402
4*4K7
4K7
R410
1N4148
4RA4005
3
6
2
7
1
8
G
V401
H
V400
H
C
GND
IN_P1[1]
IN_P1[2]
GND
IN_P1[3]
IN_P1
3E3
V418
V419
V420
V421
V422
V423
BZM55B6V2
BZM55B6V2
BZM55B6V2
BZM55B6V2
BZM55B6V2
B
BZM55B6V2
S3*6/2,54/TSM
B
Rev. Date
Name
1
06.03.2008 Ar
Title
hitex
Input Protection
DEVELOPMENT TOOLS
This document may not be passed
on, duplicated or its contents utilized,
unless expressly permitted. Violating
this stipulation will result in the liability
to pay damages. All rights reserved
in case of a patent registration or
registered design.
GND
A
12
11
10
9
8
7
6
5
4
3
Board
A
RS-EDP-DIO54-A1
Sheet
04
of
06
File modified 02.04.2008 15:40:00
2
1
12
11
10
9
8
7
6
5
4
3
2
1
H
H
G
1
1
1
G
1
DO0-L
DO1-L
DO2-L
DO3-L
VCC
EDP_DO
OUT_P0
F
EDP_DO[0]
B501
EDP_DO[1]
B502
1 2
1 2
B503
EDP_DO[2]
1 2
3
OUT_P0[0]
3
OUT_P0[1]
DO
RA500
3C5
1
2
3
4
2E8
8
7
6
5
+12V
4*1K
9
1
2
3
4
5
6
7
OUT_P0[2]
3
B504
EDP_DO[3]
1 2
OUT_P0[3]
3
U502
COM
E
1B
1C
2B
2C
3B
3C
4B
4C
5B
5C
6B
6C
7B
7C
ULN2003AD
2H12, 3A11
8
16
15
14
13
12
11
10
12VGND DO[0]
DO[1]
F
DO[2]
DO[3]
E
B505
EDP_DO[4]
C
1 2
B506
EDP_DO[5]
1 2
B507
EDP_DO[6]
1 2
1
1
2
3
4
5
6
7
OUT_P0[5]
3
OUT_P0[6]
3
B508
EDP_DO[7]
9
OUT_P0[4]
3
1 2
OUT_P0[7]
3
D
+12V
4*1K
1RA5028
2
7
3
6
4
5
1
D
1
VCC
1
DO4-L
DO5-L
DO6-L
DO7-L
E
U503
COM
E
1B
1C
2B
2C
3B
3C
4B
4C
5B
5C
6B
6C
7B
7C
ULN2003AD
NAND7
8
16
15
14
13
12
11
10
12VGND
DO[4]
DO[5]
C
DO[6]
6G4
B
B
X500
B509
1
1
2
EDP12VGND
1
2A5, 2A8
Rev. Date
Name
1
06.03.2008 Ar
2
2
This document may not be passed
on, duplicated or its contents utilized,
unless expressly permitted. Violating
this stipulation will result in the liability
to pay damages. All rights reserved
in case of a patent registration or
registered design.
12VGND
A
11
10
9
8
Output Drivers (Part 1)
DEVELOPMENT TOOLS
LM3.5/2/90
12
Title
hitex
7
6
5
4
3
Board
A
RS-EDP-DIO54-A1
Sheet
05
of
06
File modified 02.04.2008 15:40:00
2
1
12
11
10
9
8
7
6
5
4
3
2
1
VCC
H
OUT_P1
1
1
+12V
3C1
4*1K
EDP_DO
1RA6008
2
7
3
6
4
5
2E8, 2D5
1
1
DO8-L
DO9-L
DO10-L
DO11-L
H
9
G
NAND7
5B4
EDP_DO[8]
B602
EDP_DO[9]
B603
EDP_DO[10]
B604
EDP_DO[11]
B605
1 2
1 2
1 2
1 2
3
OUT_P1[0]
3
OUT_P1[1]
3
OUT_P1[2]
3
OUT_P1[3]
1
2
3
4
5
6
7
U603
COM
E
1B
1C
2B
2C
3B
3C
4B
4C
5B
5C
6B
6C
7B
7C
ULN2003AD
DO
8
16
15
14
13
12
11
10
12VGND
2H12
G
DO[7]
DO[8]
DO[9]
DO[10]
F
F
E
E
1RA6028
2
7
3
6
4
5
D
C
EDP_DO[12]
B606
EDP_DO[13]
B607
EDP_DO[14]
B608
EDP_DO[15]
B609
1 2
1 2
1 2
1 2
3
OUT_P1[4]
3
OUT_P1[5]
3
OUT_P1[6]
3
OUT_P1[7]
1
1
1
+12V
9
4*1K
1
DO12-L
DO13-L
DO14-L
DO15-L
VCC
1
2
3
4
5
6
7
U604
COM
E
1B
1C
2B
2C
3B
3C
4C
4B
5B
5C
6B
6C
7C
7B
ULN2003AD
D
8
16
15
14
13
12
11
10
12VGND
DO[10]
DO[11]
DO[12]
DO[13]
DO[14]
DO[15]
C
R627
R628
R629
VCC
B
1K0
1K0
1K0
B
EDP_DO[16]
R630
100R
DO16_L
EDP_DO[17]
R631
100R
DO17_L
2G12
Rev. Date
Name
1
06.03.2008 Ar
2G9
Title
hitex
Output Drivers (Part 2)
DEVELOPMENT TOOLS
EDP_DO[18]
A
2D5
12
R632
DO18_L
100R
EDP_DO
11
10
9
8
This document may not be passed
on, duplicated or its contents utilized,
unless expressly permitted. Violating
this stipulation will result in the liability
to pay damages. All rights reserved
in case of a patent registration or
registered design.
2G12
7
6
5
4
3
Board
A
RS-EDP-DIO54-A1
Sheet
06
of
06
File modified 02.04.2008 15:40:00
2
1
Assembly Plan Top
4*4K7
RA402
V417
1N4148
B408
B409
B410
B411
1N4148
DO0-L
DO4-L
DO8-L
DO12-L
1N4148
DO1-L
DO5-L
DO9-L
DO13-L
V414 1N4148
DO2-L
DO6-L
DO10-L DO14-L
DO3-L
DO7-L
DO11-L DO15-L
V416
V415
S3*6/2,54/TSM
J400
J401
D300
R338
120R
47R
R337
ULN2003AD
U503
X202
B602
B603
U603
ULN2003AD
ULN2003AD
U604
B509
S2*12/2.54/SMD
B609
B608
S2*10/2,54/TSM
LM3.5/2/90
LED_RGB_3216
68R
R336
B314
B312
B313
B505
B506
X203
B504 4*1K B508 4*1K B605 4*1K B606 4*1K
B503 RA500 B507 RA502 B604 RA600 B607 RA602
B501
B502
U502
ULN2003AD
X204
B415
B414
B413
B412
S2*10/2,54/TSM
X500
S2*10/2,54/TSM
X205
S3*6/2,54/TSM
B
Directory
: EDP Modules
Variant
: --
Module
: RS-EDP-DIO54-A1
Document
: BPL
Status
: 1
Usage
: external
Date / Name
: 02.04.2008 / Ar
Page
: 1/2
Hitex Development Tools
Assembly Plan Bottom
RA401
4*10K
1N4148
W X
B406
74HC14PW
1N4148
C300
B304
B302 B303
RA404
4*4K7
X201
S2*50/S/AMP
B407
Y Z
4*10K
RA403
U401
V427 1N4148
RA300
V426 1N4148 4*100R
RA301
V4254*100R
PCF8575TS
V424
1N4148
U300
RA302
4*100R
RA303
4*100R
C401
10K
R416
R417
10K
1N4148V412
Q R S T U V
1N4148V413
O P
V402
V403
1N4148
C403
1n
74HC14PW
B404
RA405
I J K 4*10K
L M N
V401
10K
R300
B301
X200
S2*70/S/AMP
U400
V400
B400
B401
B402
B403
4*4K7
RA400
1N4148
C400
E F
B405
V408
BZM55B6V2
BZM55B6V2
V411
1N4148
V405
1n
G H C405
V404 1N4148
A B C D
1N4148
A:
B:
C:
D:
E:
F:
G:
H:
I:
J:
K:
L:
M:
N:
O:
P:
Q:
R:
S:
T:
U:
V:
W:
X:
Y:
Z:
V410 BZM55B6V2
V409 BZM55B6V2
V406 BZM55B6V2
V407 BZM55B6V2
R405 10K
R404 10K
R411 4K7
R410 4K7
R435 180R
R434 180R
C404 1n
C402 1n
R432 180R
R433 180R
V431 BZM55B6V2
V430 BZM55B6V2
V423 BZM55B6V2
V422 BZM55B6V2
V421 BZM55B6V2
V418 BZM55B6V2
V419 BZM55B6V2
V420 BZM55B6V2
V428 BZM55B6V2
V429 BZM55B6V2
R423 4K7
R422 4K7
B306 B305
B307
C301
RA307
4*100R
U302 PCA9306DP1
4K7
B311 R335
B310 R334
4K7
R333
220K
RA306
4*100R
C302
U301
B309
PCF8575TS
4*100R
B308
RA304
RA305
4*100R 1K0
R627 R630 100R
R629
B300
R632
R628 1K0
1K0
100R
R631
100R
B
All capacitors without value indication: 100n
Directory
: EDP Modules
Variant
: --
Module
: RS-EDP-DIO54-A1
Document
: BPL
Status
: 1
Usage
: external
Date / Name
: 02.04.2008 / Ar
Page
: 2/2
Hitex Development Tools