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Download PEF 82902 - Digi-Key
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PEF 82902 Functional Description Figure 14 shows the timing of looping TSa from DU to DD via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD. Figure 15 shows the timing of shifting data from TSa to TSb on DU(DD). In Figure 15a) shifting is done in one frame because TSa and TSb didn’t succeed directly one another (a = 0...9 and b ≥ a+2). In Figure 15b) shifting is done from one frame to the following frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller than a (b < a). At looping and shifting the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and STOV are explained in the section ’Synchronous Transfer’. If there is no controller intervention the looping and shifting is done autonomously. •. FSC DU TSa TSa µC DD *) TSa STOV ACK WR RD STI CDAxy TSa *) if access by the µC is required Figure 14 Data Sheet Data Access when Looping TSa from DU to DD 33 2001-11-09
