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Section 9-5
Instruction Execution Times and Number of Steps
Instruction
Mnemonic
Code
Length
(steps)
Execution time (µs)
CPU6@H
CPU6@S
CPU4@S
(Duplex
(Single
(Single
CPU)
CPU)
CPU)
Conditions
CONVERT
ADDRESS
FROM CV
CONVERT
ADDRESS TO
CV
FRMCV
284
3
13.6
13.6
19.9
---
TOCV
285
3
11.9
11.9
17.2
---
DISABLE
PERIPHERAL
SERVICING
ENABLE
PERIPHERAL
SERVICING
IOSP
287
1
(See note
2.)
13.9
19.8
---
IORS
288
1
(See note
2.)
63.6
92.3
---
Note
1. When a double-length operand is used, add 1 to the value shown in the
length column in the following table.
2. Not supported by Duplex CPU Systems.
9-5-29 Block Programming Instructions
Instruction
Mnemonic
Code
Length
(steps)
Execution time (µs)
CPU6@H
CPU6@S
CPU4@S
(Duplex
(Single
(Single
CPU)
CPU)
CPU)
Conditions
BLOCK PROGRAM BEGIN
BPRG
096
2
12.1
12.1
13.0
---
BLOCK PROGRAM END
BLOCK PROGRAM PAUSE
BEND
801
1
9.6
9.6
12.3
---
BPPS
811
2
10.6
10.6
12.3
---
BLOCK PROGRAM
RESTART
CONDITIONAL
BLOCK EXIT
BPRS
812
2
5.1
5.1
5.6
---
Execution
condition
806
1
10.0
10.0
11.3
EXIT condition satisfied
4.0
4.0
4.9
EXIT condition not
satisfied
CONDITIONAL
BLOCK EXIT
EXIT (bit
address)
6.8
6.8
13.5
4.7
4.7
7.2
EXIT condition satisfied
EXIT condition not
satisfied
CONDITIONAL
BLOCK EXIT
(NOT)
EXIT NOT
(bit
address)
806
12.4
12.4
14.0
EXIT condition satisfied
7.1
7.1
7.6
Branching
Execution
condition
802
1
4.6
4.6
4.8
EXIT condition not
satisfied
IF true
802
2
802
2
6.7
6.8
9.0
7.1
9.2
6.7
6.8
9.0
7.1
9.2
7.3
7.2
9.6
7.6
10.1
IF false
IF true
IF false
IF true
IF false
Branching
Branching
(NOT)
382
EXIT
IF
IF (relay
number)
IF NOT
(relay number)
806
2
2