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P a g e | 19 Port Name clk200 rst200 enable serial_in data_out read_ack data_av Direction Input Input Input Input Output Input Output # Bit 1 1 1 1 48 1 1 Description std_logic; the clk200 frequency is 200 MHz. std_logic; synchronous rest. std_logic; std_logic; data bit from serial decoder. std_logic_vector(47 downto 0); 48 bit data from D-RORC std_logic; std_logic; Table 5-12: I/O details for Single Channel Receiver.
