Download Xilinx Vivado Design Suite Tutorial: Programming and Debugging

Debugging with Vivado™ ILA 2.0 and
Integrated Logic Analyzer
Introduction
In this tutorial exercise, you will quickly learn how to debug your FPGA designs by inserting
an Integrated Logic Analyzer (ILA) core using the Vivado™ Integrated Design Environment
(IDE). You will take advantage of integrated Vivado logic analyzer functions to debug and
discover some potential root causes of your design, thereby allowing you to quickly address
issues.
Example RTL designs will be used to illustrate overall integration flows between Vivado
logic analyzer, ILA 2.0, and Vivado IDE. In order to be successful using this tutorial, you
should have some basic knowledge of Xilinx® ISE® Design Suite and Vivado Design Suite
tool flows.
Prerequisites
A basic knowledge of Xilinx ISE Design Suite and Vivado Design Suite tool flows.
Objectives
This tutorial:
•
Shows you how to take advantage of integrated Vivado logic analyzer features in the
Vivado design environment that make the debug process faster and simpler.
•
Provides specifics on how to use the Vivado Integrated Design Environment (IDE) and
the Vivado logic analyzer to debug some common problems in FPGA logic designs.
After completing this tutorial, you will be able to:
•
Validate and debug your design using the Vivado Integrated Design Environment and
the Integrated Logic Analyzer (ILA) core.
Debugging with ChipScope
UG936 (v2012.4) December 18, 2012
www.xilinx.com
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