Download Vivado Design Suite Tutorial: Programming and Debugging

Lab 4: Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design
13. Click OK in the Specify Top Module dialog box after ensuring that the top level module is correct.
Figure 52: Specify sinegen_demo as the top level module
Step 5: Add (more) Debug Nets to the Project
1. In Vivado IDE, in the Flow Navigator, select Open Synthesized Design from the Netlist Analysis
folder.
2. Select the Netlist tab in the Netlist window to expand Nets. Select the following nets for
debugging:
•
GPIO_BUTTONS_c(2)
•
sine (20)
•
sineSel (2)
After selecting all the nets mentioned above click Mark Debug.
Figure 53: Mark additional signals for debug
Programming and Debugging
UG936 (v 2014.2) June 4, 2014
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