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Component-Level Design 279
be included in the sequence, prior to the reset of the state variable, such
as a CRC check on program memory, a range check on any important
variables, and/or verification of specific output controls.
With the last part of the design, the error task is finally defined. A
state machine design for the error task can now be completed using the
design techniques shown at the beginning of the chapter. As with the
other system designs, the various states will be defined, and the triggering
events that cause a state change. Individual actions are then defined for
each of the states and the input and output pathways are cataloged.
Appropriate changes and additions are then made to the communications plan, to accommodate the new monitoring and control functions
added to the task’s list of responsibilities. The timing chosen for the error task should also be reviewed in light of the new responsibilities the
task will have. Finally, the priority list should be reviewed to determine
whether or not the error task will be active at all times to handle any
errors the system might encounter.
Once the design is complete, the appropriate notes are added to the
design notes for the system, the error task, the system communications
plan, and the documentation on the priority-handling systems.
The last class of errors to be handled are hard errors. These errors are
so severe that the system must be either reset through a power down or by
repair of the system. In either event, the configuration of the system will
be lost, and the user will be required to completely restart and reconfigure
the software. For our design example, we have three hard errors:
List 4.8
Hard Error
Fault:
Watchdog timer timeout.
Test:
Hardware supervisor circuits.
Response: System is reset.
System will power up in error mode.
Hard Error
Fault:
Brownout reset.
Test:
Hardware supervisor circuits.
Response: System is reset, and held in reset until power is restored.
System will power up in error mode.