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Chapter 5:
Undertow Reference Manual
Generating A Dump File (VCD) From Verilog
The Verilog $dumpvars command generates the Value Change Dump File (VCD). This file
contains two main parts:
•
The definitions section defines the hierarchy of the design, and all signals defined in the
design.
•
The data section defines the changes in those signals over time.
The $dumpfile system task specifies the VCD file name. This task uses only one parameter, a
string containing the name of the file to create. If you omit this task, the name defaults to
verilog.dump. Execute this command once, before any $dumpvars tasks.
To specify which variables to dump, the $dumpvars task can include zero, one, or two
parameters.
•
If you do not include any parameters, then Undertow dumps all variables in your design.
•
To dump all variables in a specific module and all its submodules, use the module
instantiation name as a parameter in the $dumpvars command.
•
To dump all variables in a module, down to a specific level of submodules, execute the
$dumpvars command with two parameters:
•
The number of levels to dump.
•
The module to dump.
You can execute as many $dumpvars commands as you need, but you must execute all of
them at the same simulation time.
For example:
initial begin
// dump values to mydesign.dump
$dumpfile (mydesign.dump);
// dump all variables in module adder_2
// and all its submodules
$dumpvars(adder_2);
// add all variables in module adder_3 only
$dumpvars(1, adder_3);
// add all variables in module adder_4 and
// only the submodules adder_4 instantiates
$dumpvars(2, adder_4);
// add all of the variables in the design
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