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Errata Sheet
Functional Deviations
current values of FCX and LCX, thus achieving similar functionality to the
SYSCON.FCDSF flag.
In the case where the CSA list is dynamically managed, no reliable workaround
is possible.
CPU_TC.108 Incorrect Data Size for Circular Addressing mode instructions with wrap-around
In certain situations where a Load or Store instruction using circular addressing
mode encounters the circular buffer wrap-around condition, the first access to
the circular buffer may be performed using an incorrect data size, causing too
many or too few data bytes to be transferred. The circular buffer wrap-around
condition occurs when a load or store instruction using circular addressing
mode addresses a data item which spans the boundary of a circular buffer, such
that part of the data item is located at the top of the buffer, with the remainder
at the base. The problem may occur in one of two cases:
Case 1
Where a store instruction using circular addressing mode encounters the
circular buffer wrap-around condition, and is preceded in the LS pipeline by a
multi-access load instruction, the first access of the store instruction using
circular addressing mode may incorrectly use the transfer data size from the
second part of the multi-access load instruction. A multi-access load instruction
occurs in one of the following circumstances:
•
•
•
Unaligned access to LDRAM or cacheable address which spans a 128-bit
boundary.
Unaligned access to a non-cacheable, non-LDRAM address.
Circular addressing mode access which encounters the circular buffer wraparound condition.
Since half-word store instructions must be half-word aligned, and st.a
instructions must be word aligned, they cannot trigger the circular buffer wraparound condition. As such, this case only affects the following instructions using
circular addressing mode: st.w, st.d, st.da.
TC1797, QS-AC
16/115
Rel. 1.4, 25.01.2011