Download FASTFRAME 1300

•
VID_CLK – Selectable Video Clock from CLK Generator
•
PCI_CLK (33MHz for secondary PCI interface or Primary Master)
•
UART_CLK (6.144 MHz for UART timing)
IX.
INTERRUPTS
The interrupts from the various devices on the FastFrame 1300 board are connected as
shown below.
PMC Site
C
A
A
B
C
B
PCI FPGA
D
C
TriMedia
Host Connector
A
D + LED
Figure 6 – Interrupt Connections
•
This configuration allows flexible connection between host, PMC and TriMedia
interrupt sources (open drain), and handlers via the PCI FPGA.
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The TriMedia interrupt “D” pin is also connected to an LED for debugging purposes.
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