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NetFusion-EXP Ethernet SWITCH Development-Kit Reference Guide
V1.0 – July 2015
13.16 Core AXI
In the SOM sheet of the design, there exists an IP core used for AXI memory bus accessing. It does not
have any memory core attached as default when you open and view the project initially. However, this
stub is the user to use to attach to any AXI memory bus interface IP core that they wish to use. All of the
signals not used are either tied LOW (or HIGH if required) for input signals, and marked as unused if
output signals.
The AXI core is instantiated as [COREAXI_0] in the SOM sheet design and currently has no intended
functionality other than providing the user with a hook access point to the AXI ARM MSS system. The AXI
core has an associated location in the overall ARM AHB matrix memory map and therefore attached IP
cores can then have hardware address visibility from the ARM processor software environment.
Figure 44 - AMBA Memory Interfaces from ARM for an AXI bus
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