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Mixed-Language Simulation Mapping Data Types VHDL SystemC inout sc_inout<T>, sc_inout_resolved, sc_inout_rv<W> buffer sc_out<T>, sc_out_resolved, sc_out_rv<W> VHDL to SystemC State Mapping VHDL states are mapped to sc_logic, sc_bit, and bool as follows: std_logic sc_logic sc_bit bool 'U' 'X' '0' false 'X' 'X' '0' false '0' '0' '0' false '1' '1' '1' true 'Z' 'Z' '0' false 'W' 'X' '0' false 'L' '0' '0' false 'H' '1' '1' true '-' 'X' '0' false SystemC to VHDL State Mapping SystemC type bool is mapped to VHDL boolean as follows: bool VHDL false false true true SystemC type sc_bit is mapped to VHDL bit as follows: ModelSim SE User’s Manual, v6.3h July 2008 sc_bit VHDL '0' '0' '1' '1' 355
