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Standard Delay Format (SDF) Timing Annotation Disabling Timing Checks Disabling Timing Checks ModelSim offers a number of options for disabling timing checks on a "global" or individual basis. The table below provides a summary of those options. See the command and argument descriptions in the Reference Manual for more details. Table 24-21. Disabling Timing Checks Command and argument Effect tcheck_set modifies reporting or X generation status on one or more timing checks tcheck_status prints to the Transcript the current status of one or more timing checks vlog +notimingchecks disables timing check system tasks for all instances in the specified Verilog design vlog +nospecify disables specify path delays and timing checks for all instances in the specified Verilog design vopt +notimingchecks removes all timing check entries from the design as it is parsed; fixes the TimingChecksOn generic for all Vital models to FALSE; As a consequence, using vsim +notimingchecks at simulation may not have any effect on the simulation depending on the optimization of the model. vsim +no_neg_tchk disables negative timing check limits by setting them to zero for all instances in the specified design vsim +no_notifier disables the toggling of the notifier register argument of the timing check system tasks for all instances in the specified design vsim +no_tchk_msg disables error messages issued by timing check system tasks when timing check violations occur for all instances in the specified design vsim +notimingchecks disables Verilog and VITAL timing checks for all instances in the specified design; sets generic TimingChecksOn to FALSE for all VHDL Vital models with the Vital_level0 or Vital_level1 attribute. Setting this generic to FALSE disables the actual calls to the timing checks along with anything else that is present in the model's timing check block. vsim +nospecify disables specify path delays and timing checks for all instances in the specified design ModelSim SE User’s Manual, v6.3h July 2008 697
